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rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 1 R8830 16-bit risc microcontroller user?s manual rdc risc dsp controller rdc semiconductor co., ltd http:\\www.rdc.com.tw tel. 886-3-666-2866 fax 886-3-563-1498
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 2 contents 1. features ...................................................................................................................... 6 2. block diagram........................................................................................................... 7 3. pin configu ration...................................................................................................... 8 3.1 pqfp....................................................................................................................... .......................8 3.2 lqfp....................................................................................................................... .......................9 3.3 R8830 pqfp & lqpf pin-out table .........................................................................................10 4. pin descri ption ........................................................................................................ 11 4.1 R8830 i/o characteristics of each pin...................................................................................... ..16 5. basic application system block............................................................................. 19 6. read/write timi ng diagr am ................................................................................. 20 7. crystal charac teristics ........................................................................................... 22 8. execution unit ......................................................................................................... 23 8.1 general registers.......................................................................................................... ...............23 8.2 segment registers .......................................................................................................... .............24 8.3 instruction pointer and st atus flags registers ............................................................................2 4 8.4 address generation ......................................................................................................... ............26 9. peripheral control block registers ...................................................................... 27
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 3 10. power save & power down.................................................................................... 29 11. reset.......................................................................................................................... 32 12. bus interface unit ................................................................................................... 34 12.1 memory and i/o interface .................................................................................................. .........34 12.2 data bus.................................................................................................................. .....................34 12.3 wait states ............................................................................................................... ....................35 12.4 bus hold .................................................................................................................. ....................35 12.5 bus width ................................................................................................................. ...................38 13. chip select unit....................................................................................................... 39 13.1 ucs ............................................................................................................................... ..............39 13.2 lcs ............................................................................................................................... ..............40 13.3 mcsx ............................................................................................................................... ............41 13.4 pcsx ............................................................................................................................... ............43 14. interrupt contro ller unit ....................................................................................... 44 14.1 master mode and slave mode................................................................................................ .....44 14.2 interrupt vector, type and priority ....................................................................................... ......46 14.3 interrupt requests........................................................................................................ ................46 14.4 interrupt acknowledge ..................................................................................................... ...........47 14.5 programming the registers................................................................................................. .........47 15. dma un it................................................................................................................. 61 15.1 dma operation ............................................................................................................. ..............61 15.2 external requests ......................................................................................................... ...............66 15.3 serial port/dma transfer .................................................................................................. .........68 16. timer control unit ................................................................................................. 69
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 4 16.1 timer/counter unit output mode ............................................................................................ ...73 17. watchdog ti mer...................................................................................................... 75 18. asynchronous s erial port....................................................................................... 77 18.1 serial port flow control.................................................................................................. ............77 18.1.1 dce/dte protocol............................................................................................................... ...........................78 18.1.2 cts/rtr pr otocol............................................................................................................... ............................78 18.2 dma transfer to/from a serial port function ............................................................................79 18.3 the asynchronous modes description .......................................................................................7 9 19. pio unit ................................................................................................................... 84 19.1 pio multi-function pin list table......................................................................................... .....84 20. psram control unit.............................................................................................. 88 21. instruction set opcode s and clock cycles.......................................................... 89 22. R8830 execution timings....................................................................................... 93 23. dc characteristics .................................................................................................. 94 23.1 absolute maximum rating................................................................................................... .......94 23.2 recommended dc operating conditions ...................................................................................94 23.3 dc electrical characteristics............................................................................................. ..........94 24. ac characteristics .................................................................................................. 95 25. thermal charac teristics....................................................................................... 104 26. package info rmation............................................................................................. 105
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 5 26.1 pqfp...................................................................................................................... ....................105 26.2 lqfp...................................................................................................................... ....................106 27. revision hi story .................................................................................................... 107
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 6 16-bit microcontroller with 8-bit external data bus 1. features risc architecture static design & synthesizable design bus interface - multiplexed address and data bus which is compatible with 80c188 microprocessor - supports non-multiplexed address bus [a19:a0] - 1m-byte memory address space - 64k-byte i/o space software compatible with the 80c186 supports two asynchronous serial channels with hardware handshaking signals. supports serial ports with dma transfers supports cpu id supports 32 pio pins psram (pseudo static ram) interface with auto-refresh control three independent 16-bit timers and one independent watchdog timer the interrupt controller with seven maskable external interrupts and one non-maskable external interrupt two independent dma channels programmable chip-select logic for memory or i/o bus cycle decoder programmable wait-state generator
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 7 2. block diagram dma unit psram control unit chip select unit refresh control unit bus interface unit pio unit timer control unit interrupt control unit clock and power management asynchro- nous serial port0 instruction queue (64bits) instruction decoder register file general, segment, eflag register alu (special, logic, adder, bsf) micro rom ea / la address control signal execution unit x1 x2 clkouta clkoutb int6-int4 int0 tmrin0 tmrout0 tmrin1 tmrout1 drq0 drq1 txd0 rxd0 a19~a0 ad7~ad0 ao15~ao8 rd vcc gnd lcs/once0 mcs3/rfsh ucs/once1 pcs5/a1 pcs6/a2 ardy srdy s2~s0 dt/r den hold hlda s6/clkdiv2 uzi ale asynchro- nous serial port1 rts0/rtr0 cts0/enrx0 txd1 rxd1 rts1/rtr1 cts1/enrx1 rfsh2/aden wr wb int3/inta1/irq int2/inta0 int1/select nmi rst mcs2-mcs0 pcs3-pcs0 pio31~0
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 8 3. pin configuration 3.1 pqfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 R8830 rxd0/pio23 txd0/pio22 ale ardy gnd x1 x2 vcc clkouta clkoutb gnd a19/pio9 a18/pio8 vcc a17/pio7 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 vcc a0 gnd gnd hlda hold srdy/pio6 nmi int4/pio30 int0 vcc gnd vcc gnd tmrin1/pio0 tmrout1/pio1 tmrout0/pio10 tmrin0/pio11 drq1/int6/pio13 drq0/int5/pio12 ad0 ao8 ad1 ao9 ad2 ao10 ad3 a011 ad4 ao12 ad5 gnd ao13 ad6 vcc ao14 ad7 ao15 txd1/pio27 rxd1/pio28 int3/inta1/irq ucs/once1 lcs/once0 s6/clkdiv2/pio29 dt/r/pio4 den/pio5 mcs0/pio14 mcs1/pio15 int2/inta0/pio31 pcs6/a2/pio2 pcs5/a1/pio3 pcs1/pio17 pcs0/pio16 mcs2/pio24 mcs3/rfsh/pio25 rst uzi/pio26 wr rd s2 s1 s0 int1/select pcs2/cts1/enrx1/pio18 pcs3/rts1/rtr1/pio19 rts0/rtr0/pio20 cts0/enrx0/pio21 wb rfsh2/aden
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 9 3.2 lqfp R8830 ad0 ao8 ad1 ao9 ad2 ao10 ad3 ao11 ad4 ao12 ad5 gnd ao13 ad6 vcc ao14 ad7 ao15 s6/clkdiv2/pio29 uzi/pio26 txd1/pio27 rxd1/pio28 rxd0/pio23 txd0/pio22 wr rd ale ardy s1 s0 gnd x1 x2 vcc clkouta clkoutb gnd a19/pio9 a18/pio8 vcc a17/pio7 a16 a15 a14 a13 a12 a11 a9 a10 a8 a7 a6 a4 a5 a3 a2 vcc a0 a1 gnd hold hlda srdy/pio6 nmi int4/pio30 int0 vcc gnd vcc gnd tmrin1/pio0 tmrout0/pio10 tmrin0/pio11 tmrout1/pio1 drq1/int6/pio13 drq0/int5/pio12 dt/r/pio4 int3/inta1/irq int2/inta0/pio31 int1/select lcs/once0 pcs6/a2/pio2 pcs5/a1/pio3 pcs1/pio17 pcs0/pio16 rst 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 55 54 53 52 51 60 59 58 57 56 65 64 63 62 61 70 69 68 67 66 75 74 73 72 71 76 77 78 80 79 81 82 83 85 84 86 87 88 90 89 91 92 93 95 94 96 97 98 100 99 den/pio5 mcs3/rfsh/pio25 cts0/enrx0/pio21 rts0/rtr0/pio20 gnd pcs3/rts1/rtr1/pio19 pcs2/cts1/enrx1/pio18 rfsh2/aden s2 wb mcs0/pio14 mcs1/pio15 ucs/once1 mcs2/pio24
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 10 3.3 R8830 pqfp & lqpf pin-out table pin name lqfp pin no. pqfp pin no. pin name lqfp pin no. pqfp pin no. ad0 1 78 a11 51 28 ao8 2 79 a10 52 29 ad1 3 80 a9 53 30 ao9 4 81 a8 54 31 ad2 5 82 a7 55 32 ao10 6 83 a6 56 33 ad3 7 84 a5 57 34 ao11 8 85 a4 58 35 ad4 9 86 a3 59 36 ao12 10 87 a2 60 37 ad5 11 88 vcc 61 38 gnd 12 89 a1 62 39 ao13 13 90 a0 63 40 ad6 14 91 gnd 64 41 vcc 15 92 gnd 65 42 ao14 16 93 wb 66 43 ad7 17 94 hlda 67 44 ao15 18 95 hold 68 45 s6/ 2 clkdiv /pio29 19 96 srdy/pio6 69 46 uzi /pio26 20 97 nmi 70 47 txd1/pio27 21 98 dt/ r /pio4 71 48 rxd1/pio28 22 99 den /pio5 72 49 0 cts / 0 enrx /pio21 23 100 0 mcs /pio14 73 50 rxd0/pio23 24 1 1 mcs /pio15 74 51 txd0/pio22 25 2 int4/pio30 75 52 0 rts / 0 rtr /pio20 26 3 int3/ 1 inta /irq 76 53 2 rfsh / aden 27 4 int2/ 0 inta /pio31 77 54 wr 28 5 int1/ select 78 55 rd 29 6 int0 79 56 ale 30 7 ucs / 1 once 80 57 ardy 31 8 lcs / 0 once 81 58 2 s 32 9 6 pcs /a2/pio2 82 59 1 s 33 10 5 pcs /a1/pio3 83 60 0 s 34 11 vcc 84 31 gnd 35 12 3 pcs / 1 rts / 1 rtr /pio19 85 62 x1 36 13 2 pcs / 1 cts / 1 enrx /pio18 86 63 x2 37 14 gnd 87 64 vcc 38 15 1 pcs /pio17 88 65 clkouta 39 16 0 pcs /pio16 89 66 clkoutb 40 17 vcc 90 67 gnd 41 18 2 mcs /pio24 91 68 a19/pio9 42 19 3 mcs / rfsh /pio25 92 69 a18/pio8 43 20 gnd 93 70 vcc 44 21 rst 94 71 a17/pio7 45 22 tmrin1/pio0 95 72 a16 46 23 tmrout1/pio1 96 73 a15 47 24 tmrout0/pio10 97 74 a14 48 25 tmrin0/pio11 98 75 a13 49 26 drq1/int6/pio13 99 76 a12 50 27 drq0/int5/pio12 100 77
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 11 4. pin description pin no. (pqfp) symbol type description 15, 21, 38, 61, 67, 92 vcc input system power: +5 volt power supply. 12, 18, 41, 42 64, 70, 89 gnd input system ground. 71 rst input reset input. when rst is asserted, the cpu immediately terminates all operations, clears the internal registers & logic, and transfers the address to the reset address ffff0h. 13 x1 input input to the oscillator amplifier. 14 x2 output output from the inverted oscillator amplifier. 16 clkouta output clock output a. the clkouta operation is the same as that of crystal input frequency (x 1). clkouta remains active during reset and bus hold conditions. 17 clkoutb output clock output b. the clkoutb operation is the same as that of crystal input frequency (x1). clkoutb remains active during reset and bus hold conditions. asynchronous serial port interface 1 rxd0/pio23 input/output receive data for asynchronous serial port 0. this pin receives asynchronous serial data. 2 txd0/pio22 output/input transmit data for asynchronous serial port 0. this pin transmits asynchronous serial data from the uart of the microcontrollers. 3 0 rts / 0 rtr /pio20 output/input ready to send/ready to recei ve signal for asynchronous serial port 0. when the rts0 bit in the auxcon register is set and the fc bit in the serial port 0 control register is set, the 0 rts signal is enabled. ot herwise, when the rts0 b it is cleared and the fc bit is set, the 0 rtr signal is enabled. 100 0 cts / 0 enrx /pio21 input/output clear to send/enable receiver request signal for asynchronous serial port 0. when the enrx0 b it in the auxcon register is cleared and th e fc bit in the serial port 0 control register is set, the 0 cts signal is enabled. otherwise, when the enrx0 bit is set and the fc bit is set, the 0 enrx signal is enabled. 98 txd1/pio27 output/input transmit data for asynchronous serial port 0. this pin transmits asynchronous serial data from the uart of the microcontrollers. 99 rxd1/pio28 input/output receive data for asynchronous serial port 0. this pin receives asynchronous serial data. 62 3 pcs / 1 rts / 1 rt r output/input ready to send/ready to recei ve signal for asynchronous serial port 1. when the rts1 bit in the auxcon register is set and the fc bit in the serial port 1 register is set, the 1 rts signal is enabled. otherwise, when the rts1 bit is cleared and the fc bit is set, the 1 rtr signal is enabled. 63 2 pcs / 1 cts / 1 enrx output/input clear to send/enable r eceiver request signal for asynchronous serial port 0. when the enrx1 bit in the auxcon register is cleared and th e fc bit in the serial port 0 control register is set, the 1 cts signal is enabled. otherwise, when the enrx1 bit is set and the fc bit is set, the 1 enrx signal is enabled.
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 12 bus interface 4 2 rfsh / aden output/input for 2 rfsh feature, this pin is active low to indicate a dram refresh bus cycle. for aden feature, when this pin is held high on power-on reset, the address portion of the ad bus can be disabled or enabled by the da bit in the lmcs and umcs register during lcs or ucs bus cycle access. the 2 rfsh / aden is with a weak internal pull-up resistor, so no external pull-up resistor is required. the ad bus always drives both address and data during lcs or ucs bus cycle access if the 2 rfsh / aden pin is with an external pull-low resistor during reset. 5 wr output write strobe. this pin indicates that the data on the bus is to be written into a memory or an i/o device. wr is active during t2, t3 and tw of any write cycle, floating during a bus hold or reset. 6 rd output read strobe. it's an active low signal which indicates that the microcontroller is performing a memory or i/o read cycle. rd is floating during a bus hold or reset. 7 ale output addressed latch enable. active high. this pin indicates that an address output on the ad bus. address is guaranteed to be valid on the trailing edge of ale. this pin is tri-stated during once mode and is never floating during a bus hold or reset. 8 ardy input asynchronous ready. this pin performs the microcontroller that the address memory space or i/o device will complete a data transfer. the ardy pin accepts a rising edge that is asynchronous to clkouta and is active high. the falling edge of ardy must be synchronized to clkouta. tie ardy high, so the microcontroller is always asserted in the ready condition. if the ardy is not used, tie this pin low to yield control to srdy. both srdy and ardy should be tied to high if the system need not assert wait states by externality. bus cycle status. these pins ar e encoded to indicate the bus status. 2 s can be used as memory or i/o indicator. 1 s can be used as dt/ r indicator. these pins are floating during hold and reset. bus cycle encoding description 2 s 1 s 0 s bus cycle 9 10 11 2 s 1 s 0 s output 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 interrupt acknowledge read data from i/o write data to i/o halt instruction fetch read data from memory write data to memory passive 19 20 22 23-37 39, 40 a19/pio9 a18/pio8 a17/pio7 a16-a2 a1, a0 output/input address bus. non-multiplexed mem ory or i/o address. the a bus is one-half of a clkouta period earlier than the ad bus. these pins are high-impedance during a bus hold or reset. 78,80,82,84, 86, ad0-ad7 input/output the multiplexed address and data bus for memory or i/o accessin g . the address is p resent durin g the t1 clock p hase, and
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 13 88,91,94 the data bus phase is in t2-t4 cycle. the address phase of the ad bu s can be disabled when the 2 rfsh / aden pin is with an external pull-low resistor during reset. the ad bus is in high-impedance state during bus hold or reset conditions and this bus is also used to load system configuration information (with pull-up or pull-low resistors) into the rescon(f6h) register when the reset input goes from low to high. 79,81,83,85, 87,90 93,95 ao8-ao15 output address only bus, in the multiplexed address bus, the ao15 ? ao8 combine with the ad7 ? ad0 to form a 16- b it address bus. these pins are floating during a bus hold or reset. 43 wb output write byte. this pin is active low to indicate a write cycle on the bus. it is floating during reset. 44 hlda output bus hold acknowledge. active high. the microcontroller will issue an hlda in response to a hold request by external bus master at the end of t4 or ti. when the microcontroller is in hold status (hlda is high), the ao15-ao8, ad7-ad0, a19-a0, wr , rd , den , 0 s - 1 s , s6, 2 rfsh , dt/ r , and wb are floating, and the ucs , lcs , 6 pcs - 5 pcs , 3 mcs - 0 mcs and 3 pcs - 0 pcs will be driven high. after hold is detected as being low, the microcontroller will lower hlda. 45 hold input bus hold request. active high. this pin indicates that another bus master is requesting the local bus. 46 srdy/pio6 input/output synchronous ready. this pin performs the microcontroller that the address memory space or i/o device will complete a data transfer. the srdy pin accepts a falling edge that is asynchronous to clkouta and is active high. srdy is accomplished by elimination of the one-half clock period required to internally synchronize ardy. tie srdy high, so the microcontroller is always asserted in the ready condition. if the srdy is not used, tie this pin low to yield control to ardy. both srdy and ardy should be tied to high if the system need not assert wait states by externality. 48 dt/ r /pio4 output/input data transmit or receive. this pin indicates the direction of data flow through an external data-bus transceiver. when dt/ r is asserted low, the microcontroller receives data. when dt/r is asserted high, the microcontroller writes data to the data bus. 49 den /pio5 output/input data enable. this pin is provided as a data bus transceiver output enable. de n is asserted during memory and i/o access. de n is driven high when dt/ r changes states. it is floating during bus hold or reset conditions. 96 s6/ 2 clkdiv /pio29 output/input bus cycle status bit6/clock divided by 2. for s6 feature, this pin is low to indicate a microcontroller-initiated bus cycle or high to indicate a dma-initiated bus cycle during t2, t3, tw and t4. for 2 clkdiv feature, the internal clock of microcontroller is the external clock divided by 2. (clkouta, clkoutb=x1/2) if this pin is held low during power-on reset. the pin is sampled on the rising edge of rst . 97 uzi /pio26 output/input upper zero indicate. this pin is the logical or of the inverted a19 a16 i i d iht1 dihldh h h
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 14 a19-a16. it is asserted in the t1 and is held throughout the cycle. chip select unit interface 50 51 68 69 0 mcs /pio14 1 mcs /pio15 2 mcs /pio24 3 mcs / rfsh /pio25 output/input midrange memory chip selects. for mcs feature, these pins are active low when the mmcs(a6h) register is enabled to access a memory. the address ranges are programmable. 3 mcs - 0 mcs are held high during bus holds. when the lmcs (a2h) register is programmed, pin69 is as a rfsh pin to auto refresh the psram. 57 ucs / 1 once output/input upper memory chip select/once mode request 1. for ucs feature, this pin is active low when system accesses the defined portion memory block of the upper 512k-byte (80000h-fffffh) memory region. ucs default active address region is from f0000h to fffffh after power-on reset. the address range for ucs is programmed by software. for 1 once feature, if 0 once and 1 once are sampled low on the rising edge of rst . the microcontroller enters once mode. in once mode, all pins are high-impedance. this pin incorporates a weak pull-up resistor. 58 lcs / 0 once output/input lower memory chip select/once mode request 0. for lcs feature, this pin is active low when the microcontroller accesses the defined portion memory block of the lower 512k (00000h-7ffffh) memory region. the address range for lcs is programmed by software. for 0 once feature, see ucs / 1 once description. this pin incorporates a weak pull-up resistor. 59 60 6 pcs /a2/pio2 5 pcs /a1/pio3 output/input peripheral chip selects/latched address bit. for pcs feature, these pins are active low when the microcontroller accesses the fifth or sixth region of the peripheral memory (i/o or memory space). the base address of pcs is programmable. these pins are asserted with the ad address bus and are not floating during bus holds. for latched address bit feature. these pins output the latched address a2 and a1 when the ex bit is cleared in the pcs and mcs auxiliary register. the a2 and a1 retains previous latched data during bus holds. 62 63 65 66 3 pcs / 1 rts / 1 rt r /pio19 2 pcs / 1 cts / 1 enrx pio18 1 pcs /pio17 0 pcs /pio16 output/input peripheral chip selects. these pins are actilve low when the microcontroller accesses the defined memory area of the peripheral memory block (i/o or memory address). for i/o accessed, the base address can be programmed in the region 00000h to 0ffffh. for memory address access, the base address can be located in the 1m-byte memory address region. these pins are asserted with the multiplexed ad address bus and are not floating during bus holds. interrupt control unit interface 47 nmi input non-maskable interrupt. the nmi is the highest priority hardware interrupt and is non-maskable. when this pin is asserted (nmi transition from low to high), the microcontroller always transfers the address bus to the location specified by the non-maskable interrupt vector in the microcontroller interrupt vector table. the nmi p in must be asserted for at least one
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 15 clkouta period to guarantee that the interrupt is recognized. 52 int4/pio30 input/output maskable interrupt request 4. act high. this pin indicates that an interrupt request has occu rred. the microcontroller will jump to the int4 address vector to execute the service routine if int4 is enabled. the interrup t input can be configured to be either edge- or level-triggered. the requesting device must hold int4 until the request is acknowledged to guarantee interrupt recognition. 53 int3/ 1 inta /irq input/output maskable interrupt request 3 /interrupt acknowledge 1/slave interrupt request. for int3 f eature, except the differences in interrupt line and interrupt addres s vector, the function of int3 is the same as that of int4. for 1 inta feature, in cascade mode or special fully-nested mode, this pin corresponds to int1. for irq feature, when the microc ontroller is as a slave device, this pin issues an interrupt request to the master interrupt controller. 54 int2/ 0 inta /pio31 input/output maskable interrupt request 2 /interrupt acknowledge 0. for int2 feature, except the differences in interrupt line and interrupt address vector, the function of int2 is the same as that of int4. for 0 inta feature, in cascade mode or special fully-nested mode, this pin corresponds to int0. 55 int1/ select input/output maskable interrupt request 1/sl ave select. for int1 feature, except the differences in interr upt line and interrupt address vector, the function of int1 is the same as that of int4. for select feature, when the microcontroller is as a slave device, this pin is driven from the master interrupt controller decoding. this pin us active to indicate that an interrupt appears on the address and data bus. int0 must be activated before select is activated when the interrupt type appears on the bus. 56 int0 input/output maskable interrupt request 0. except the differences in interrupt line and interrupt address vector, the function of int0 is the same as that of int4. timer control unit interface 72 75 tmrin1/pio0 tmrin0/pio11 input/output timer input. these pins can be as clock or control signal input, which depend upon the programmed timer mode. after internally synchronizing low to high transitions on tmrin, the timer controller increments. these pins must be pulled up if not being used. 73 74 tmrout1/pio1 tmrout0/pio10 output/input timer output. depending on timer mode select, these pins provide single pulse or continuous waveforms. the duty cycle of the waveform can be programmable. these pins are floating during a bus hold or reset. dma unit interface 76 77 drq1/int6/pio13 drq0/int5/pio12 input/output dma request. these pins are a sserted high by an external device when the device is ready for dma channel 1 or channel 0 to perform a transfer. these pins are level-triggered and internally synchronized. the drq signals are not latched and must remain active until finish is serviced. for int6/int5 function: when the dma function is not being used, int6/int5 can be used as an additional external interrupt request. they share the corresponding interrupt type and re g ister control bits. the int6/5 are level-tri gg ered onl y
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 16 and must not necessary to be held until the interrupt is acknowledged. (such high levels keep interrupt requests.) notes: 1. when pio mode and direction registers are set, 32 mux definition pins can be set as pio pins. for example, the drq1/int6/pio13 (pin76) can be set as pio13. 2. the pio status during power-on reset: pio1, pio10, pio22 and pio23 are input with pull-downs, pio4 to pio9 are in normal operations, and the others are input with pull-ups. 4.1 R8830 i/o characteristics of each pin pqfp pin no. pin name characteristics 71 rst schmitt trigger input, with a 50k internal pull-up resistor 8 ardy schmitt trigger input, with a 50k internal pull-down resistor 45 47 hold nmi cmos input, with a 50k internal pull-down resistor 56 55 int0 int1/ select schmitt trigger ttl input, with a 10k internal pull-down resistor 16 17 clkouta clkoutb 8ma 3-state cmos output 9 2 s bi-directional i/o, with a 50 k internal pull-up resistor 4ma ttl output 10 11 1 s 0 s 4ma 3-state cmos output 43 6 5 wb rd wr 12ma 3-state cmos output 19 20 22 a19/pio9 a18/pio8 a17/pio7 bi-directional i/o, with a 10k enabled/disabled internal pull-up resistor when functioning as pio, for normal function, the 10k pull-up resistor is disabled. 16ma ttl output 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 39 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 16ma 3-state cmos output
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 17 40 a0 78 80 82 84 86 88 91 94 79 81 83 85 87 90 93 95 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ao8 ao9 ao10 ao11 ao12 ao13 ao14 ao15 bi-directional i/o, 16ma ttl output 7 ale bi-directional i/o, with a 50 k internal pull-down resistor 4ma ttl output 46 74 73 2 1 srdy/pio6 tmrout0/pio10 tmrout1/pio1 txd0/pio22 rxd0/pio23 bi-directional i/o, with a 10k enabled/disabled internal pull-down resistor when functioning as pio, for normal function, the 10k pull-down resistor is disabled. 8ma ttl output 4 2 rfsh / aden bi-directional i/o, with a 50 k internal pull-up resistor 4ma ttl output 44 hlda 4ma cmos output 54 52 int2/ 0 inta /pio31 int4/pio30 bi-directional i/o, with a 10k enabled/disabled internal pull-up resistor when functioning as pio, for normal function, the 10k pull-up resistor is disabled. 8ma ttl output, ttl schmitt trigger input 53 int3/ 1 inta /irq bi-directional i/o, with a 10 k internal pull-up resistor 8ma ttl output, ttl schmitt trigger input 57 58 ucs / 1 once lcs / 0 once bi-directional i/o, with a 10 k internal pull-up resistor 8ma ttl output, ttl schmitt trigger input
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 18 49 48 66 65 63 62 60 59 50 51 68 69 97 96 75 72 77 76 98 99 100 3 den /pio5 dt/ r /pio4 0 pcs /pio16 1 pcs /pio17 2 pcs / 1 cts / 1 enrx /pio18 3 pcs / 1 rts / 1 rtr /pio19 5 pcs /a1/pio3 6 pcs /a2/pio2 0 mcs /pio14 1 mcs /pio15 2 mcs /pio24 3 mcs / rfsh /pio25 uzi /pio26 s6/ 2 clkdiv /pio29 tmrin0/pio11 tmrin1/pio0 drq0/int5/pio12 drq1/int6/pio13 txd1/pio27 rxd1/pio28 0 cts / 0 enrx /pio21 0 rts / 0 rtr /pio20 bi-direction i/o, with enabled/disabled 10 k internal pull-up resistor when functions as pio, for normal function, the 10k pull-up resistor is disabled. 8ma ttl output
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 19 5. basic application system block x1 x2 rs232 level converter serial port1 timer0-1 int x dma pio d7-d0 a19-a0 wr data(8) address ucs rd we oe ce flash rom data(8) address sram data address we oe peripheral cs pcs x R8830 we oe ce lcs basic application system block (b) rst vcc 100k 1uf dir transciver g latch den dt/r ad7-ad0 ad7-ad0 ale ao15-ao8 a19-a16 rs232 level converter serial port0 x1 x2 rs232 level converter serial port1 timer0-1 int x dma pio ad7-ad0 a19-a0 wr data(8) address ucs rd we oe ce flash rom data(8) address sram data address we oe peripheral cs pcs x R8830 we oe ce lcs basic application system block (a) rst vcc 100k 1uf rs232 level converter serial port0
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 20 6. read/write timing diagram clkouta a19:a0 s6 ao15:ao8 ale den dt/r uzi t1 t2 t3 t4 address ucs,lcs s2:s0 tw read cycle pcs x, mcs x address rd ad7:ad0 address data 75 7
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 21 clkouta a19:a0 s6 ao15:ao8 ale wr den dt/r uzi t1 t2 t3 t4 address ucs,lcs s2:s0 tw write cycle pcs x, mcs x address ad7:ad0 wb address data 76 7
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 22 7. crystal characteristics x1 x2 l c2 c1 rf R8830 c3 for fundamental -mode crystal: reference values frequency 10.8288mhz 19.66mhz 30mhz 33mhz 40mhz rf none none none none none c1 10pf 10pf none none none c2 10pf 10pf 10pf 10pf 10pf c3 none none none none none l none none none none none for third-overtone mode crystal: reference values frequency 22.1184mhz 28.322mhz 33.177mhz 40mhz rf 1m 1.5m 1.5m 1.5m c1 15pf 15pf 15pf 15pf c2 30pf 30pf 30pf 30pf c3 none 220pf 220pf 220pf l none 10ul 4.7ul 2.7ul
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 23 8. execution unit 8.1 general registers the R8830 has eight 16-bit general registers and the ax, bx, cx and dx can be subdivided into two 8-bit registers (ah, al, bh, bl, ch, cl, dh and dl). the functions of these registers are described as follows. ax : word divide, word multiply, word i/o operation. al : byte divide, byte multiply, byte i/o, decimal arithmetic, translate operation. ah : byte divide, byte multiply operation. bx : translate operation. cx : loops, string operation cl : variable shift and rotate operation. dx : word divide, word multiply, indirect i/o operation sp : stack operations (pop, popa, popf, push, pusha and pushf) bp : general-purpose registers which can be used to determine offset address of operands in memory. si : string operations di : string operations accumulator base register count/loop/repeat/shift data stack pointer destination index base pointer source index ax bx cx dx data group index group and pointer general registers ah bh ch dh al bl cl dl sp bp si di 0 7 8 15 high low
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 24 8.2 segment registers the R8830 has four 16-bit segment registers, cs, ds, ss and es. the segment registers contain the base addresses (starting location) of these memory segments, and they are immediately addressable for code (cs), data (ds & es) and stack (ss) memory. cs (code segment) : the cs register points to the current code segment, which contains instructions to be fetched. the default location memory space for all instructions is 64k. the initial value of cs register is 0ffffh. ds (data segment) : the ds register points to the current data segment, which generally contains program variables. the ds register is initialized to 0000h. ss (stack segment) : the ss register points to the current stack segment, which is for all stack operations, such as pushes and pops. the stack segment is used for temporar y space. the ss register is initialized to 0000h. es (extra segment) : the es register points to the current extra segment which is typically for data storage, such as large string operations and large da ta structures. the es register is initialized to 0000h. cs ds ss es 0 7 8 15 code segment data segment stack segment extra segment segment registers 8.3 instruction pointer and status flags registers ip (instruction pointer) : the ip is a 16-bit register and it contains the offset of the next instruction to be fetched. software cannot be used to directly access the ip re gister and this register is updated by the bus interface unit. it can be changed, saved or restored as a result of program execution. the ip register is initialized to 0000h and the cs:ip starting execution address is at 0ffff0h.
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 25 processor status flags registers flags 0 reset value : 0000h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 res pf res cf af res zf sf tf if df of reserved these flags reflect the status af ter the execution unit is executed. bit 15-12: reserved bit 11: of , overflow flag. if an arithmetic overflow occurs, this flag will be set. bit 10: df , direction flag. if this flag is set, the string instructi ons are in the process of incrementing addresses. if df is cleared, the string instructions are in th e process of decrementing addresses. refer to the std and cld instructions for setting and clearing the df flag. bit 9: if , interrupt-enable flag. refer to the sti and cli instructions for setting and clearing the if flag. set 1: the cpu enables the maskable interrupt requests. set 0: the cpu disables the maskable interrupt requests. bit 8: tf , trace flag. set to enable single-step mode for debuggi ng; cleared to disable th e single-step mode. if an application program sets the tf flag with popf or iret instruction, a debug exception is generated after the instruction (the cpu automatically generates an interrupt after each instruction) that follows the popf or iret instruction. bit 7: sf, sign flag. if this flag is set, the high-order bit of the result of an operation will be 1 , indicating it is negative. bit 6: zf , zero flag. if the result of operation is zero, this flag will be set. bit 5: reserved bit 4: af , auxiliary flag. if this flag is set, there will be a carry from the low nibble to the high one or a borrow from the high nibble to the low one of the al general-purpose register. it is used in bcd operation. bit 3: reserved. bit 2: pf , parity flag. if the result of low-order 8-bit operation has even parity, this flag will be set. bit 1: reserved bit 0: cf , carry flag. if cf is set, there will be a carry out or a borrow into the high-order bit of the instruction result.
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 26 8.4 address generation the execution unit generates a 20-bit physical address to bus interface unit by the a ddress generation. memory is organized in sets of segments. each segment contains a 16-bit value. memo ry is addressed with a two-component address that consists of a 16-bit segment and 16-bit offset. the physical address generati on figure describes how the logical address is transferred to the physical address. 12f90 19 0 0012 15 0 12fa2 19 0 to memory 12f9 0012 15 0 15 0 physical address segment base offset logical address shift left 4 bits physical address generation
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 27 9. peripheral control block registers the peripheral control block can be mapped into either memory or i/o space by programming the feh register and it starts at ff00h in i/o space when the microprocessor is reset. the following table is the defin itions of all the peripheral control block registers, and the detailed descriptions will be arranged on the related block unit. offset (hex) register name page offset (hex) register name page fe peripheral control block relocation register 28 70 pio mode 0 register 87 fa disable peripheral clock register 31 66 timer 2 mode/control register 72 f6 reset configuration register 33 62 timer 2 maxcount compare a register 73 f4 processor release level register 28 60 timer 2 count register 73 f2 auxiliary configuration register 38 5e timer 1 mode/control register 71 f0 power-save control register 30 5c timer 1 maxcount compare b register 72 e6 watchdog timer control register 75 5a timer 1 maxcount compare a register 72 e4 enable rcu register 88 58 timer 1 count register 72 e2 clock pre-scaler register 88 56 timer 0 mode/control register 69 e0 memory partition register 88 54 ti mer 0 maxcount compare b register 71 da dma 1 control register 65 52 timer 0 maxcount compare a register 71 d8 dma 1 transfer count register 65 50 timer 0 count register 71 d6 dma 1 destination address high register 65 46 power down configuration register 31 d4 dma 1 destination address low register 65 44 serial port 0 interrupt control register 48 d2 dma 1 source address high register 66 42 serial port 1 interrupt control register 48 d0 dma 1 source address low register 66 40 int4 control register 49 ca dma 0 control register 62 3e int3 control register 49 c8 dma 0 transfer count register 64 3c int2 control register 50 c6 dma 0 destination address high register 64 3a int1 control register 50 c4 dma 0 destination address low register 64 38 int0 control register 51 c2 dma 0 source address high register 64 36 dma 1/int6 interrupt control register 52 c0 dma 0 source address low register 65 34 dma 0/int5 interrupt control register 53 a8 pcs and mcs auxiliary register 42 32 timer interrupt control register 53 a6 midrange memory chip select register 41 30 interrupt status register 54 a4 peripheral chip select register 43 2e interrupt request register 55 a2 low memory chip select register 40 2c interrupt in-service register 56 a0 upper memory chip select register 39 2a priority mask register 57 88 serial port 0 baud rate divisor register 82 28 interrupt mask register 58 86 serial port 0 receive regist er 82 26 poll status register 59 84 serial port 0 transmit register 82 24 poll register 59 82 serial port 0 status register 81 22 end-o f-interrupt register 59 80 serial port 0 control register 79 20 interrupt vector register 60 7a pio data 1 register 85 18 serial port 1 baud rate divisor 83 78 pio direction 1 register 85 16 se rial port 1 recei ve register 83 76 pio mode 1 register 86 14 serial port 1 transmit register 83 74 pio data 0 register 86 12 serial port 1 status register 83 72 pio direction 0 register 86 10 serial port 1 control register 83
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 28 peripheral control block relocation register: offset : feh 0 reset value : 20ffh 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 res res r19 - r8 m/io s/m the peripheral control block is mapped into either memory or i/o space by programmi ng this register. when the other chip selects ( pcsx or mcsx ) are programmed to zero wait state and the external ready is ignored, the pcsx or mcsx can overlap the control block. bit 15 : reserved bit 14 : s/ m , slave/master ? configure the interrupt controller s et 0 : master mode, s et 1: slaved mode bit 13 : reserved bit 12 : m/ io , memory/io space. at reset, this bit is set to 0 and the pcb map starts at ff00h in i/o space. s et 1 - the peripheral control block (pcb) is located in memory space. s et 0 - the pcb is located in i/o space. bit 11-0 : r19-r8 , relocation address bits the upper address bits of the pcb base address. de faults for the lower eight bits default are 00h. when the pcb is mapped to i/o space, the r19-r 16 must be programmed to 0000b. processor release level register offset : f4h 0 reset value : d9h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 prl 11011001 this is a read-only register that specifies the processor release ve rsion and rdc identification number bit 15-8 : processor version 01h: version a, 02h: vers ion b, 03h: version c, 04h: version d bit 7-0 : rdc identification number - d9h
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 29 10. power save & power down x1 x2 clkin or clkin/2 clock divisior (clk/2-clk/128) mux caf(f0h.9) mux cbf(f0h.11) cad(f0h.8) cbd(f0h.10) f2-f0(f0h.2-f0h.0) psen(f0h.15) clk clkin clkin/2 select s6/clkdiv2 clkouta clkoutb microprocessor internal clock system clock enable/disable divisor select pwd(46h.15) enable/disable the cpu provides power-save & power-down functions. * power-save: in power-save mode, users can program the power-save control register to divide the internal operating clock. users can also disable each non-use peripheral cl ock by programming the disable peripheral clock register. * power-down: this cpu can enter power-down mode (stop clock) when the power down configuration register is programmed during the cpu is running in full speed mode or power-save mode. the cp u will be waked up when each one of the external int0, int1, int2, int3 and int4 pins is active high and the cpu operating clock will get back to full speed mode if the int is serviced (the interrupt flag is enabled). if the interrupt flag is disabled, the cpu will be waked up by the int, the operating clock wi ll get back to the previous operating clock st ate, and the cpu will execute the next progr am counter instruction. there is 19-bit counter time waiting the crystal clock to be stable when the cpu wakes up from the stop clock mode.
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 30 power-save control register offset : f0h 0 reset value : 0000h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 mcsbit psen 00000f2f1f0 cad caf cbd cbf 0 0 bit 15 : psen , enable power-save mode. this bit is cleared by hardware when an external interrupt occurs. this bit will not change when software interrupts (int instructions) and exceptions occur. set 1: enable power-save mode and divide the internal operating clock by the values in f2-f0. bit14: mcsbit , 0 mcs control bit. set 0: the 0 mcs operates normally. set 1: 0 mcs is active over the entire mcsx range bit13-12 : reserved bit 11 : cbf , clkoutb output frequency selection. set 1: clkoutb output frequency is the same as crystal input frequency. set 0: clkoutb output frequency is from the clock divisor, which is the same as that of microprocessor's internal clock. bit 10: cbd , clkoutb drive disable set 1: disable clkoutb. this pin will be three-stated. set 0: enable clkoutb. bit 9: caf , clkouta output fre quency selection. set 1: clkouta output frequency is the same as crystal input frequency. set 0: clkouta output frequency is from the clock divisor, which is the same as that of microprocessor's internal clock . bit 8: cad , clkouta drive disable. set 1: disable clkouta. this pin will be three-stated. set 0: enable clkouta. bit 7-3 : reserved bit 2-0: f2- f0, clock divisor select. f2, f1, f0 ----- divider factor 0, 0, 0 ---- divided by 1 0, 0, 1 ---- divided by 2 0, 1, 0 ---- divided by 4 0, 1, 1 ---- divided by 8 1, 0, 0 ---- divided by 16 1, 0, 1 ---- divided by 32 1, 1, 0 ---- divided by 64 1, 1, 1 ---- divided by 128
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 31 disable peripheral clock register offset : fah 0 reset value : 0000h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved intclk uart clk dma clk timer clk bit 15: int clk, set 1 to stop the interrupt controller clock bit 14: uart clk, set 1 to stop the asynchronous serial port controller clock bit 13: dma clk, set 1 to stop the dma controller clock bit 12: timer clk , set 1 to stop the timer controller clock bit 11-0: reserved power down configuration register offset : 46h 0 reset value : 00h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pw d 0 0 0 0 0 0 w if 0 0 0 i4 i3 i2 i1 i0 bit 15: pwd, power- down enable. when this bit is set to 1, the cpu will enter power-down mode, then the crystal clock will stop. the cpu will be waked up when an external int (int0 ? int4) is active high. it will wait 19-bit counter time for the crystal clock to be stable before the cpu is waked up. bit 14-9 : reserved bit 8: wif, wake-up interrupt flag. it's a read-only bit. when the cpu is waked up by interrupt from power-down mode, this bit will be set to 1 by hardware. otherwise this bit is 0. bit 7-5 : reserved bit 4 -0 : i4 -i0, enable the external interrupt (int4 ? int0) wake-up function. set these bits to 1 to make the int pins function as power-down wake-up pins.
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 32 11. reset processor initialization is accomp lished with activation of the rst pin. to reset the processor, this pin should be held low for at least seven oscillator periods. the reset status figure shows the status of the rst pin and other related pins. when rst goes from low to high, the state of i nput pin (with weak pull-ups or pull-dow ns) will be latched , and each pin will perform the individual function. the ao15-ao8 and ad7-ad0 will be latched into the register f6h. ucs / 1 once and lcs / 0 once will enter once mode (all of the pins will be floating except x1 and x2) when they are with pull-low resistors. the input clock w ill be divided by 2 when s6/ 2 clkdiv is with a pull-low resistor. the ad7-ad0 bus will drive both of the address and data regardless of the da bit setting during ucs and lcs cycles if 2 rfsh / aden is with a pull-low resistor. clkouta a19-a0 s6 ad7-ad0 ale bhe rd den s2-s0 ffff0 f0 7474 min 7t ucs ea reset status (float) (input) (input) (float) (float) (float) (float) (float) dt/r (input) (input) rst ff (input) ao15-ao8
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 33 reset configuration register offset : f6h 0 reset value : ao15-ao8, ad7-ad0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 rc bit 15- 0 : rc , reset configuration ao15 ? ao8, ad7 ? ad0. the ao15 to ao8, ad7 to ad0 must be with weak pull-up or pull-down resistors to correspond to the contents when ao15 to ao8 and ad7-ad0 are latched into this register as the rst pin goes from low to high. the value of the reset configuration register provides the system information when this register is read by software. this register is read-only and the contents remain valid until next processor reset.
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 34 12. bus interface unit in order to define a bus cycle, the bus interface unit drives addr ess, data, status and control in formation. the bus a19-a0 are non-multiplexed memory or i/o address. the ad7-ad0 are multip lexed address and data bus fo r memory or i/o access. the 2 s - 0 s are encoded to indicate the bus status, which is described in the pin description table in page 12. the basic application system block (page 19) and read/write timi ng diagram (page 20) describe the basic bus operation. 12.1 memory and i/o interface the memory space consists of 1m bytes and the i/o space consis ts of 64k bytes. memory devices exchange information with the cpu during memory read, memory write and instruction fetch bus cycles. i/o read and i/o write bus cycles use a separate i/o address space. only in/out instruc tion can access i/o address space, and inform ation must be transferred between the peripheral device and the ax register. the first 256 bytes of i/o space can be accessed directly by the i/o instructions. the entire 64k bytes i/o address space can be acce ssed indirectly, through the dx register. i/ o instructions always force address a19-a16 to low level. memory space fffffh 0 1m bytes i/o space 0ffffh 0 64k bytes memory and i/o space 12.2 data bus the memory address space data bus is phy sically implemented as one bank of 1m bytes. address lines a19-a0 select a specific byte within the bank. byte transfers to even or odd addr esses transfer information in one bus cycle. word transfers to even or odd addresses transfer information in two bus cycl es. the bus interface unit automa tically converts the word access into two consecutive byte accesses, making th e operation transparent to the programmer. for word transfers, the word address defines the first byte transferred. the second byte transfer occurs from the word address plus one.
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 35 fffff ffffe 2 1 0 1m bytes d7:0 a19:0 physical data bus models (x) a19:0 first bus cycle d7:0 (x+1) a19:0 second bus cycle d7:0 8-bit data bus word transfers 12.3 wait states wait states extend the data phase of the bus cycle. the ardy or srdy input with lo w level will be inserted wait states in. if r2 bit=0, users can also insert wait states by programming the in ternal chip select registers. the r2 bit of umcs (offset 0a0h) default is low, so each one of the ardy or srdy should be in ready state (with a pull high resist or) when at power on reset or external reset. the wait-state counter value is decided by the r3, r1 and r0 bits in each chip select register. there are five groups of r3, r1 and r0 bits in the registers offset a0h, a2h, a4h, a6h and a8h. each group is independent. wait state counter rising edge d q r2 bit in control registers bus ready clkouta ardy srdy wait-state block diagram bus ready is active high r2 bit in umcs default is"0", so cpu is required external ready at power-on reset. the wait state counter value is located at control registers in chip select unit. falling edge d q clkouta clkouta 12.4 bus hold when the bus hold is requested (hold pin active high) by another bus master, the microprocessor will issue an hlda in response to a hold request at the end of t4 or ti. when the microprocessor is in hold status (hlda is high), ao15-ao8, ad7-ad0, a19-a0, wr , rd , den , 1 s - 0 s , s6, 2 rfsh , dt/ r and wb are floating, and ucs , lcs , 6 pcs - 5 pcs , 3 mcs - 0 mcs and 3 pcs - 0 pcs will be driven high. after hold is detected as being low, the microprocessor will lower the hlda.
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 36 clkouta hold hlda a19:a0 den s6 s2:s0 ad7:ad0 rd wr dt/r wb bus hold enter waveform 2 7 case 1 case 2 ti t3 ti t4 ti ti ti ti floating floating floating floating floating floating floating floating floating
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 37 clkouta hold hlda a19:a0 s6 s2:s0 ad7:ad0 rd wr dt/r wb address 7 data den 6 bus hold leave waveform case 1 case 2 ti ti ti ti ti t4 t1 t1 floating floating floating floating floating floating floating floating floating ti ti
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 38 12.5 bus width the R8830 default is only 8-bit bus access dur ing memory or i/o access located in the ucs , lcs , mcs x or pcsx address space. auxiliary configuration register offset : f2h 0 reset value : 0000h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved enrx1 rts1 enrx0 rts0 reserved bit 15-7 : reserved. bit 6: enrx1 , enable the receiver request of serial port 1. set 1: the 1 cts / 1 enrx pin is configured as 1 enrx . set 0: the 1 cts / 1 enrx pin is configured as 1 cts . bit 5: rts1 , enable request to send of serial port 1. set 1: the 1 rt r / 1 rts pin is configured as 1 rts . set 0: the 1 rt r / 1 rts pin is configured as 1 rt r . bit 4: enrx0 , enable the receiver request of serial port 0. set 1: the 0 cts / 0 enrx pin is configured as 0 enrx . set 0: the 0 cts / 0 enrx pin is configured as 0 cts . bit 3: rts0 , enable request to send of serial port 0. set 1: the 0 rtr / 0 rts pin is configured as 0 rts . set 0: the 0 rtr / 0 rts pin is configured as 0 rtr . bit 2-0: reserved.
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 39 13. chip select unit the chip select unit provides 12 programmable chip select pins to access a specific me mory or peripheral device. the chip selects are programmed through five peripheral control register s (a0h, a2h, a4h, a6h and a8h) and all of the chip selects can be inserted wait states in by programming the periphe ral control register. 13.1 ucs the ucs default is active on reset for programming code access. the memory active range is upper 512k (80000h ? fffffh), which is programmable. and the default memory active range of ucs is 64k (f0000h ? fffffh). the ucs is active to drive low four clkouta oscillato rs if no wait state is inserted. ther e are three wait states inserted to ucs active cycle on reset. upper memory chip select register offset : a0h 0 reset value :f03bh 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 lb2 - lb0 0000da0111r2r1r0 bit 15 : reserved bit 14-12: lb2-lb0 , memory block size selection for ucs chip select pin. the active region of the ucs chip select pin can be configured by lb2-lb0. the default memory block size is from f0000h to fffffh. lb2, lb1, lb0 ---- memory block size , start address , end address 1 , 1 , 1 ---- 64k , f0000h , fffffh 1 , 1 , 0 ---- 128k , e0000h , fffffh 1 , 0 , 0 ---- 256k , c0000h , fffffh 0 , 0 , 0 ---- 512k , 80000h , fffffh bit 11-8 : reserved bit 7: da , disable address. if the 2 rfsh / aden pin is held high on the rising edge of rst , the da bit is valid to enable/disable the address phase of the ad bus. if the 2 rfsh / aden pin is held low on the rising edge of rst , the ad bus always drives the address and data. set 1: disable the address phase of the ad7 ? ad0 bus cycle when ucs is asserted. the ao15 ? ao8 are driven as address bus even this bit is set to 1. set 0: enable the address phase of the ad7 ? ad0 bus cycle when ucs is asserted. bit 6-3 : reserved bit 2: r2 , ready mode. this bit is used to configure the ready mode for the ucs chip select. set 1: external ready is ignored.
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 40 set 0: external ready is required. bit 1-0: r1-r0 , wait-state value. when r2 is set to 0, wait states can be inserted into an access to the ucs memory area. (r1,r0) = (0,0) -- 0 wait state ; (r1,r0) = (0,1) -- 1 wait state (r1,r0) = (1,0) -- 2 wait states ; (r1,r0) = (1,1) -- 3 wait states 13.2 lcs the lower 512k bytes (00000h-7ffffh) memory re gion chip selects. the memory active range is programmable, which has no default size on reset. so the a2h regist er must be programmed first before th e target memory range is accessed. the lcs pin is not active on reset, but any read or write access to the a2h register activates this pin. low memory chip select register offset : a2h 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 ub2 - ub0 1111dapse111r2r1r0 bit 15 : reserved bit 14-12: ub2-ub0, memory block size selection for the lcs chip select pin the active region of the lcs chip select pin can be configured by ub2-ub0. the lcs pin is not active on reset, but any read or write acce ss to the a2h (lmcs) register activates this pin. ub2, ub1, ub0 ---- memory block size , start address , end address 0 , 0 , 0 ---- 64k , 00000h , 0ffffh 0 , 0 , 1 ---- 128k , 00000h , 1ffffh 0 , 1 , 1 ---- 256k , 00000h , 3ffffh 1 , 1 , 1 ---- 512k , 00000h , 7ffffh bit 11-8: reserved bit 7: da , disable address. if the 2 rfsh / aden pin is held high on the rising edge of rst , the da bit is valid to enable/disable the address phase of the ad bus. if the 2 rfsh / aden pin is held low on the rising edge of rst , the ad bus always drives the address and data. set 1: disable the address pha se of the ad7 ? ad0 bus cycle when lcs is asserted. the ao15 ? ao8 are driven as address bus even this bit is set to 1. set 0: enable the address pha se of the ad7 ? ad0 bus cycle when lcs is asserted. bit 6: pse , psram mode enable. this bit is us ed to enable psram support for the lcs chip select memory space. the refresh control unit registers e0h, e2h a nd e4h must be configured for auto re fresh before psram support is enabled. pse set to 1: psram support is enabled. pse set to 0: psram support is disabled. bit 5-3 : reserved
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 41 bit 2: r2 , ready mode. this bit is used to configure the ready mode for the lcs chip select. set 1: external ready is ignored. set 0: external ready is required. bit 1-0: r1-r0 , wait-state value. when r2 is set to 0, wait states can be inserted into an access to the lcs memory area. (r1,r0) = (0,0) -- 0 wait state ; (r1,r0) = (0,1) -- 1 wait state (r1,r0) = (1,0) -- 2 wait states ; (r1,r0) = (1,1) -- 3 wait states 13.3 mcsx the memory block of mcs3 - mcs0 can be located anywhere within the 1m-b yte memory space, exclusive of the areas associated with the ucs and lcs chip selects. the maximum mcsx active memory range is 512k bytes. the 512k mcsx block size can only be used when located at address 00000h, and the lcs chip select must not be active in this case. locating a 512k mcsx block size at 80000h always c onflicts with the range of ucs and is not allowed. the mcsx chip selects are programmed through two regi sters a6h and a8h, and these select pins are not active on reset. both a6h and a8h registers must be accessed with a read or write to activate mcs3 - mcs0 . there aren?t default values on a6h and a8h registers, so a6h and a8h must be programmed first before mcs3 - mcs0 are active. midranage memory chip select register offset : a6h 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ba19 - ba13 1 1 1 1 r2 r1 r0 1 1 bit 15-9: ba19-ba13 , base address. the ba19-ba13 correspond to bits 19-13 of the 1m-byte (20-bits) programmable base address of the mcs chip select block. the bits 12 to 0 of the base address are always 0. the base address can be set to any integer multiple of the size of the memory block size selected in thes e bits. for example, if the midrange block is 32kbytes, only the bits ba19 to ba15 can be pr ogrammed. so the block addr ess could be locate at 20000h or 38000h but not at 22000h. the base address of the mcs chip select can be set to 00000h only if the lcs chip select is not active. the mcs chip select address range is not allowed to overlap the lcs chip select address range. the mcs chip select address range is also not allowed to overlap the ucs chip select address range. bit 8-3 : reserved bit 2: r2 , ready mode. this bit is configured to enab le/disable the wait states inserted for the mcs chip selects. the r1 and r0 bits of this register determ ine the number of wait states to be inserted. set 1: external ready is ignored. set 0: external ready is required. bit 1-0: r1-r0 , wait-state value. the r1 and r0 determine the number of wait states inserted into a mcs access. (r1,r0) : (1,1) ? 3 wait states , (1,0) ? 2 wait states, (0,1) ? 1 wait state , (0,0) ? 0 wait state
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 42 offset : a8h 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 m6 - m0 ms 1 1 1 r2 r1 r0 ex 1 pcs and mcs auxiliary register bit 15, 5-3 : reserved bit 14-8: m6-m0 , mcs block size. these bits determine the total block size for the mcs3 - mcs0 chip selects. each individual chip select is active for one quarter of the total block size. for exam ple, if the block size is 32k bytes and the base address is located at 20000h, the individual active memory address range of mcs3 to mcs0 is mcs0 ? 20000h to 21fff, mcs1 -22000 to 23fffh, mcs2 - 24000h to 25fffh and mcs3 - 26000h to 27fffh. mcsx total block size is defined by m6-m0, m6-m0 , total block size , mcsx address active range 0000001b , 8k , 2k 0000010b , 16k , 4k 0000100b , 32k , 8k 0001000b , 64k , 16k 0010000b , 128k , 32k 0100000b , 256k , 64k 1000000b , 512k , 128k bit 7: ex , pin selector. this bit configur es the multiplexed output which the pcs6 - pcs5 pins are as chip selects or a2-a1. set 1: pcs6 and pcs5 are configured as peri pheral chip select pins. set 0: pcs6 is configured as address bit a2, pcs5 is configured as a1. bit 6: ms , memory or i/o space selector. set 1: the pcsx pins are active for memory bus cycle. set 0: the pcsx pins are active for i/o bus cycle. bit 2: r2 , ready mode. this bit is configured to enable/d isable the wait states inserted for the pcs5 and pcs6 chip selects. the r1 and r0 bits of this register de termine the number of wait states to be inserted. set 1: external ready is ignored. set 0: external ready is required. bit 1-0: r1-r0 , wait-state value. the r1,r0 determines th e number of wait states inserted into a pcs5 - pcs6 access. (r1,r0) : (1,1) ? 3 wait states , (1,0) ? 2 wait st ates, (0,1) ? 1 wait states , (0,0) ? 0 wait states
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 43 13.4 pcsx in order to define these pins, the peri pheral or memory chip selects are progra mmed through the a4h and a8h registers. the base address memory block can be located anywhere within the 1m-byte memory space, exclusive of the areas associated with the ucs , lcs and mcs chip selects. if the chip selects are mappe d to i/o space, the access range is 64k bytes. pcs6 ? pcs5 can be configured from 0 wait-state to 3 wait-states. pcs3 ? pcs0 can be configured from 0 wait-state to 15 wait-states. peripheral chip select register offset : a4h 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ba19 - ba11 1 1 1 r3 r2 r1 r0 bit 15-7: ba19-ba11 , base address. ba19-ba11 correspond to bit 19-11 of the 1m-byte (20-bits) programmable base address of the pcs chip select block. when the pcs chip selects are mapped to i/o space, ba19- ba16 must be written to 0000b because the i/o address bus is only 64k bytes (16-bits) wide. pcs x address range: pcs0 : base address - base address+255 pcs1 : base address+256 - base address+511 pcs2 : base address+512 - base address+767 pcs3 : base address+768 - base address+1023 pcs5 : base address+1280 - base address+1535 pcs6 : base address+1536 - base address+1791 bit 6-4 : reserved bit 3: r3 ; bit 1-0: r1, r0 ,wait-state value. the r3, r1 and r0 determ ine the number of wait-states inserted into a pcs3 - pcs0 access. r3, r1, r0 -- wait states 0, 0, 0 -- 0 0, 0, 1 -- 1 0, 1, 0 -- 2 0, 1, 1 -- 3 1, 0, 0 -- 5 1, 0, 1 -- 7 1, 1, 0 -- 9 1, 1, 1 -- 15 bit 2 : r2 , ready mode. this bit is configured to enab le/disable the wait states inserted for the pcs3 - pcs0 chip selects. the r3, r1 and r0 bits determine the number of wait states to be inserted. set 1: external ready is ignored set 0: external ready is required
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 44 14. interrupt controller unit there are 16 interrupt request sources conn ected to the controller: 7 maskable inte rrupt pins (int0 ? int6); 2 non-maskable interrupts (nmi and wdt); 7 internal unit request sources (timer 0, 1 and 2; dma 0 and 1; as ynchronous serial port 0 and 1). interrupt control logic 0 0 0 1 1 1 master/slave mode select (feh.14) timer0/1/2 interrupt req. timer0 req. int0 timer1 req. timer2 req. dma0 interrupt req. dma1 interrupt req. int2 int3 int4 asynchronous serial port 0 execation unit interrupt type interrupt req. in-service register eoi register acknowledge acknowledge to dma, timer,serial port unit internal address/data bus 16 bit 16 bit interrupt control unit block diagram asynchronous serial port 1 int5 int6 nmi nmi watchdog timer int1 14.1 master mode and slave mode the interrupt controller can be programmed as a master or sl ave mode. (to program feh, bit 14), the master mode has two connections: fully nested mode conn ection or cascade mode connection.
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 45 R8830 interrupt source int0 int1 int2 int3 int4 interrupt source interrupt source interrupt source interrupt source fully nested mode connections int5 int6 interrupt source interrupt source cascade mode connection int0 inta0 int1 inta1 8259 ir7 8259 ir7 cas3-cas0 cas3-cas0 R8830 8259 cas3-cas0 8259 cas3-cas0 int inta int inta interrupt sources interrupt sources interrupt sources interrupt sources int4 int5 int6 slave mode connection int0 inta0 irq 8259 R8830 cascade address dccode select
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 46 14.2 interrupt vector, type and priority the following table shows the interrupt vector addresses, types and the priority. the ma skable interrupt priority can be change d by programming the priority register. the vect or addresses for each interrupt are fixed. interrupt source interrupt type vector address eoi type priority note divide error exception 00h 00h 1 trace interrupt 01h 04h 1-1 * nmi 02h 08h 1-2 * breakpoint interrupt 03h 0ch 1 into detected over flow exception 04h 10h 1 array bounds exception 05h 14h 1 undefined opcode exception 06h 18h 1 esc opcode exception 07h 1ch 1 timer 0 08h 20h 08h 2-1 */** reserved 09h dma 0/int5 0ah 28h 0ah 3 ** dma 1/int6 0bh 2ch 0bh 4 ** int0 0ch 30h 0ch 5 int1 0dh 34h 0dh 6 int2 0eh 38h 0eh 7 int3 0fh 3ch 0fh 8 int4 10h 40h 10h 9 asynchronous serial port 1 11h 44h 11h 9 timer 1 12h 48h 08h 2-2 */** timer 2 13h 4ch 08h 2-3 */** asynchronous serial port 0 14h 50h 14h 9 reserved 15h-1fh note *: when the interrupt occurs in the same time, the priority is (1-1 > 1-2); (2-1> 2-2 > 2-3) note **: the interrupt types of these sources are programmable in slave mode. 14.3 interrupt requests when an interrupt is requested, the internal interrupt controller verifies that the inte rrupt is enabled (the if flag is enable d and no msk bit set) and that there are no higher priority interrupt requests being serviced or pending. if the interrupt is granted , the interrupt controller uses the interrupt type to access a vector from the interrupt vector table. if the external int is active (level-triggere d) to request the interrupt controller serv ice, and the int pins must be held till the microcontroller enters the interrupt servi ce routine. there is no interrupt-acknowle dge output when running in fully nested mode, so the pio pins should be used to simu late the interrupt-acknowledge pin if necessary.
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 47 14.4 interrupt acknowledge the processor requires the interrupt type as an index into the interrupt table. the internal interrupt can provide the interrup t type or an external controller can provide the interrupt type. the internal interrupt controller provides the interrupt type to processor without external bus cycle gene ration. when an external interrupt cont roller is providing the interrupt type, the processor generates two acknowledge bus cy cles, and the interrupt type is written to the ad7-ad0 lines by the external interrupt controller. 7 070 clkouta address[19:0] s6 ad7:ad0 ale den s2:s0 interrupt acknowledge cycle (casecade or slave mode) intr ack intr ack address dt/r t1 t2 t3 t4 t1 t2 t3 t4 interrupt type inta0,inta1 14.5 programming the registers software is used to program the registers ( master mode: 44h, 42h, 40h, 3eh, 3ch, 3ah, 38h, 36h, 34h, 32h, 30h, 2eh, 2ch, 2ah, 28h, 26h, 24h and 22h; slave mode: 3ah, 38h, 36h, 34h, 32h, 30h, 2eh, 2ch, 2ah, 28h, 22h and 20h ) to define the interrupt controller operation.
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 48 serial port 0 interrupt control register offset : 44h 0 reset value : 001fh 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved 1 msk pr2 pr1 pr0 (master mode) bit 15-4 : reserved bit 3: msk , mask. set 1: mask the interrupt sour ce of the asynchronous serial port 0. set 0: enable the serial port 0 interrupt. bit 2-0: pr2-pr0 , priority. these bits determine the priority of the serial ports relate d to the other interrupt signals. the priority selection: pr2 , pr1 , pr0 -- priority 0 , 0 , 0 -- 0 ( high) 0 , 0 , 1 -- 1 0 , 1 , 0 -- 2 0 , 1 , 1 -- 3 1 , 0 , 0 -- 4 1 , 0 , 1 -- 5 1 , 1 , 0 -- 6 1 , 1 , 1 -- 7 ( low ) serial port 1 interrupt control register offset : 42h 0 reset value : 000fh 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved msk pr2 pr1 pr0 (master mode) bit 15-4 : reserved bit 3: msk , mask. set 1: mask the interrupt sour ce of the asynchronous serial port 1. set 0: enable the serial port 1 interrupt. bit 2-0: pr2-pr0 , priority. these bits determine the priority of the serial ports relate d to the other interrupt signals. the priority selection: pr2 , pr1 , pr0 -- priority 0 , 0 , 0 -- 0 ( high) 0 , 0 , 1 -- 1 0 , 1 , 0 -- 2 0 , 1 , 1 -- 3 1 , 0 , 0 -- 4 1 , 0 , 1 -- 5 1 , 1 , 0 -- 6 1 , 1 , 1 -- 7 ( low )
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 49 int4 control register offset : 40h 0 reset value : 000fh 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved msk pr2 pr1 pr0 ltm etm reserved (master mode) bit 15- 8: reserved bit 7: etm , edge trigger enable. when this bit is set to 1 and bit 4 set to 0, an interrupt is triggered by a low to high edge. bit 6-5: reserved bit 4: ltm , level-triggered mode. set 1: an interrupt is tri ggered by high active level. set 0: an interrupt is triggered by the low to high edge. bit 3: msk , mask. set 1: mask the interrupt source of int4 set 0: enable the int4 interrupt. bit 2-0: pr , interrupt priority these bit settings for priority sel ection are the same as those of bit 2-0 of 44h. int3 control register offset : 3eh 0 reset value : 000fh 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved msk pr2 pr1 pr0 ltm etm reserved (master mode) bit 15- 8: reserved bit 7: etm , edge trigger enable. when this bit is set to 1 and bit 4 set to 0, an interrupt is triggered by a low to high edge. bit 6- 5: reserved bit 4: ltm , level-triggered mode. set 1: an interrupt is triggered by high active level. set 0: an interrupt is triggered by the low to high edge. bit 3: msk , mask. set 1: mask the interrupt source of int3. set 0: enable the int3 interrupt. bit 2-0: pr , interrupt priority these bit settings for priority sel ection are the same as those of bit 2-0 of 44h.
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 50 int2 control register offset : 3ch 0 reset value : 000fh 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved msk pr2 pr1 pr0 ltm etm reserved (master mode) bit 15- 8, bit 6-5: reserved bit 7: etm , edge trigger enable. when this bit is set to 1 and bit 4 set to 0, an interrupt is triggered by a low to high edge. bit 4: ltm , level-triggered mode. set 1: an interrupt is triggered by high active level. set 0: an interrupt is triggered by the low to high edge. bit 3: msk , mask. set 1: mask the interrupt source of int2 set 0: enable the int2 interrupt. bit 2-0: pr , interrupt priority these bit settings for priority sel ection are the same as those of bit 2-0 of 44h. int1 control register offset : 3ah 0 reset value : 000fh 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved msk pr2 pr1 pr0 ltm c sfnm etm (master mode) bit 15-8: reserved bit 7: etm , edge trigger enable. when this bit is set to 1 and bit 4 set to 0, an interrupt is triggered by a low to high edge. bit 6: sfnm, special fully nested mode. set 1: enable the special fully nested mode of int1. bit 5: c, cascade mode. set this bit to 1 to en able the cascade mode for int1 or int0. bit 4: ltm , level-triggered mode. set 1: an interrupt is triggered by high active level. set 0: an interrupt is triggered by the low go high edge. bit 3: msk , mask. set 1: mask the interrupt source of int1. set 0: enable the int1 interrupt. bit 2-0: pr , interrupt priority these bit settings for priority sel ection are the same as those of bit 2-0 of 44h.
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 51 int1 control register offset : 3ah 0 reset value : 0000h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved msk pr2 pr1 pr0 (slave mode), this register is for timer 2 interrupt control, reset value is 0000h bit 15- 4: reserved bit 3: msk , mask. set 1: mask the interrupt source of timer 2 set 0: enable the timer 2 interrupt. bit 2-0: pr , interrupt priority these bit settings for priority sel ection are the same as those of bit 2-0 of 44h. int0 control register offset : 38h 0 reset value : 000fh 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved msk pr2 pr1 pr0 ltm c sfnm etm (master mode) bit 15-8: reserved bit 7: etm , edge trigger enable. when this bit is set to 1 and bit 4 set to 0, an interrupt is triggered by a low to high edge. bit 6: sfnm, special fully nested mode. set 1: enable the special fully nested mode of int0. bit 5: c, cascade mode. set this bit to 1 to en able the cascade mode for int1 or int0. bit 4: ltm , level-triggered mode. set 1: an interrupt is tri ggered by high active level. set 0: an interrupt is triggered by the low to high edge. bit 3: msk , mask. set 1: mask the interrupt source of int0. set 0: enable the int0 interrupt. bit 2-0: pr , interrupt priority these bit settings for priority sel ection are the same as those of bit 2-0 of 44h.
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 52 int0 control register offset : 38h 0 reset value : 0000h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved msk pr2 pr1 pr0 (slave mode), for timer 1 interrupt control register, reset value is 0000h bit 15-4 : reserved bit 3: msk , mask. set 1: mask the interrupt source of timer 1 set 0: enable the timer 1 interrupt. bit 2-0: pr , interrupt priority these bit settings for priority sel ection are the same as those of bit 2-0 of 44h. dma 1/int6 interrupt control register offset : 36h 0 reset value : 000fh 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 msk pr2 pr1 pr0 0 0 0 0 0 0 0 0 0 0 0 0 (master mode) bit 15-4 : reserved bit 3: msk , mask. set 1: mask the interrupt source of the dma 1 controller set 0: enable the dma 1 controller interrupt. bit 2-0: pr , interrupt priority these bit settings for priority sel ection are the same as those of bit 2-0 of 44h. dma 1/int6 interrupt control register offset : 36h 0 reset value : 0000h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 msk pr2 pr1 pr0 0 0 0 0 0 0 0 0 0 0 0 0 (slave mode) bit 15-4 : reserved bit 3: msk , mask. set 1: mask the interrupt source of the dma 1 controller set 0: enable the dma 1 controller interrupt. bit 2-0: pr , interrupt priority these bit settings for priority sel ection are the same as those of bit 2-0 of 44h.
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 53 dma 0/int5 interrupt control register offset : 34h 0 reset value : 000fh 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 msk pr2 pr1 pr0 0 0 0 0 0 0 0 0 0 0 0 0 (master mode) bit 15-4 : reserved bit 3: msk , mask. set 1: mask the interrupt source of the dma 0 controller set 0: enable the dma 0 controller interrupt. bit 2-0: pr , interrupt priority these bit settings for priority sel ection are the same as those of bit 2-0 of 44h. dma 0/int5 interrupt control register offset : 34h 0 reset value : 0000h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 msk pr2 pr1 pr0 0 0 0 0 0 0 0 0 0 0 0 0 (slave mode) bit 15-4 : reserved bit 3: msk , mask. set 1: mask the interrupt source of the dma 0 controller set 0: enable the dma 1 controller interrupt. bit 2-0: pr , interrupt priority these bit settings for priority sel ection are the same as those of bit 2-0 of 44h. timer interrupt control register offset : 32h 0 reset value : 000fh 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 msk pr2 pr1 pr0 0 0 0 0 0 0 0 0 0 0 0 0 (master mode) bit 15-4 : reserved bit 3: msk , mask. set 1: mask the interr upt source of the timer controller set 0: enable the timer controller interrupt. bit 2-0: pr , interrupt priority these bit settings for priority sel ection are the same as those of bit 2-0 of 44h.
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 54 timer interrupt control register offset : 32h 0 reset value : 0000h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 msk pr2 pr1 pr0 0 0 0 0 0 0 0 0 0 0 0 0 (slave mode) bit 15-4 : reserved bit 3: msk , mask. set 1: mask the interrupt source of the timer 0 controller set 0: enable the timer 0 controller interrupt. bit 2-0: pr , interrupt priority these bit settings for priority sel ection are the same as those of bit 2-0 of 44h. interrupt status register offset : 30h 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved tmr2 tmr1 tmr0 dhlt (master mode) , reset value undefined bit 15: dhlt , dma halt. set 1: halt any dma activity when non-maskable interrupts occur. set 0: when an iret instruction is executed. bit 14-3: reserved. bit 2-0: tmr2-tmr0 , set 1: indicate the corresponding tim er has an interrupt request pending. interrupt status register offset : 30h 0 reset value : 0000h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved tmr2 tmr1 tmr0 dhlt (slave mode) bit 15: dhlt , dma halt. set 1: halt any dma activity when non-maskable interrupts occur. set 0: when an iret instruction is executed. bit 14-3: reserved. bit 2-0: tmr2-tmr0 , set 1: indicate the corresponding timer has an interrupt request pending.
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 55 interrupt request register offset : 2eh 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved d0/i5 res tmr d1/i6 i0 i1 i2 i3 i4 sp1 sp0 (master mode) the interrupt request register is a r ead-only register. for internal interrupt s (sp0, sp1, d1/i6, d0/i5 and tmr), the corresponding bit is set to 1 when the device requests an interr upt. the bit is reset during the internally generated interrupt acknowledge. for int4-int0 external interr upts, the corresponding bit (i4-i0) reflects th e current value of the external signal . bit 15-11: reserved. bit 10: sp0 , serial port 0 interrupt re quest. indicate the interrupt st ate of the serial port 0. bit 9: sp1 , serial port 1 interrupt re quest. indicate the interrupt st ate of the serial port 1. bit 8-4: i4-i0 , interrupt requests. set 1: the corresponding int pi n has an interrupt pending. bit 3-2: d1/i6-d0/i5 , dma channel or int interrupt request. set 1: the corresponding dma channel or int has an interrupt pending. bit 1: reserved. bit 0: tmr , timer interrupt request. set 1: the timer control unit has an interrupt pending. interrupt request register offset : 2eh 0 reset value : 0000h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved d0/i5 res tmr0 d1/i6 tmr1 tmr2 (slave mode) the interrupt request register is a read -only register. for internal interrupts (d 1/i6, d0/i5, tmr2, tmr1 and tmr0), the corresponding bit is set to 1 when the device requests an interr upt. the bit is reset during the internally generated interrupt acknowledge. bit 15-6: reserved. bit 5-4: tmr2/tmr1 , timer2/timer1 interrupt request. set 1: indicate the state of any interr upt requests form the associated timer. bit 3-2: d1/i6-d0/i5 , dma channel or int interrupt request. set 1: indicate the corresponding dma cha nnel or int has an interrupt pending. bit 1: reserved. bit 0: tmr0 , timer 0 interrupt request. set 1: indicate the state of an interrupt request from timer 0.
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 56 interrupt in-service register offset : 2ch 0 reset value : 0000h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved d0/i5 res tmr d1/i6 i0 i1 i2 i3 i4 sp1 sp0 (master mode) the bits in the inserv register are set by the interrupt controller when the interrupt is taken. each bit in the register is cl eared by writing the corresponding interrupt type to the eoi register. bit 15-11: reserved. bit 10: sp0 , serial port 0 interrupt in-service. set 1: the serial port 0 interr upt is currently being serviced. bit 9: sp1 , serial port 1 interrupt in-servi ce. set 1: the serial port 1 interr upt is currently being serviced. bit 8-4: i4-i0 , interrupt in-service. set 1: the corresponding int interr upt is currently being serviced. bit 3-2: d1/i6-d0/i5 , dma channel or int interrupt in-service. set 1: the corresponding dma channel or in t interrupt is currently being serviced. bit 1: reserved. bit 0: tmr , timer interrupt in-service. set 1: the tim er interrupt is currently being serviced. interrupt in-service register offset : 2ch 0 reset value : 0000h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved d0/i5 rsvd tmr0 d1/i6 tmr1 tmr2 (slave mode) the bits in the in-service register are set by the interrupt controller wh en the interrupt is taken. the in- s ervice bits are cleared by writing to the eoi register. bit 15-6: reserved. bit 5-4: tmr2-tmr1 , timer2/timer1 interrupt in-service. set 1: the corresponding timer interr upt is currently being serviced. bit 3-2: d1/i6-d0/i5 , dma channel or int interrupt in-service. set 1: the corresponding dma channel or in t interrupt is currently being serviced. bit 1: reserved. bit 0: tmr0 , timer 0 interrupt in-service. set 1: the timer 0 interrupt is currently being serviced.
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 57 priority mask register offset : 2ah 0 reset value : 0007h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 prm2 prm1 prm0 0 0 0 0 0 0 0 0 0 0 0 0 0 (master mode) it determines the minimum priority level at whic h maskable interrupts can generate an interrupt. bit 15-3: reserved. bit 2-0: prm2-prm0 , priority field mask. it determines the minimum pr iority that is required in order for a maskable interrupt source to generate an interrupt. priority pr2-pr0 (high) 0 000 1 001 2 010 3 011 4 100 5 101 6 110 (low) 7 111 priority mask register offset : 2ah 0 reset value : 0007h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 prm2 prm1 prm0 0 0 0 0 0 0 0 0 0 0 0 0 0 (slave mode) it determines the minimum priority level at whic h maskable interrupts can generate an interrupt. bit 15-3: reserved. bit 2-0: prm2-prm0 , priority field mask. it determines the minimum pr iority that is required in order for a maskable interrupt source to generate an interrupt. priority pr2-pr0 (high) 0 000 1 001 2 010 3 011 4 100 5 101 6 110 (low) 7 111
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 58 interrupt mask register offset : 28h 0 reset value : 07fdh 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 d0/i5 res tmr d1/i6 i0 i1 i2 i3 i4 sp1 sp0 reserved (master mode) bit 15-11: reserved. bit 10: sp0 , serial port 0 interrupt mask. the state of the ma sk bit of the asynchronous serial port 0 interrupt. bit 9: sp1 , serial port 1 interrupt mask. the state of the ma sk bit of the asynchronous serial port 1 interrupt. bit 8-4: i4-i0 , interrupt masks. indicates the state of the mask bit of the corresponding interrupt. bit 3-2: d1/i6-d0/i5 , dma channel or int interrupt masks. indicates the state of the mask b it of the corresponding dma channel or int interrupt. bit 1: reserved. bit 0: tmr , timer interrupt mask. the state of th e mask bit of the timer control unit . interrupt mask register offset : 28h 0 reset value : 003dh 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved d0/i5 res tmr0 d1/i6 tmr1 tmr2 (slave mode) bit 15-6: reserved. bit 5-4: tmr2-tmr1 , timer 2/timer1 interrupt mask. the state of the mask bit of the timer interrupt control register. set 1: timer2 or time1 has its interrupt requests masked bit 3-2: d1/i6-d0/i5 , dma channel or int interrupt mask. indicate the state of the mask bits of the corresponding dma or in t6/int5 control register. bit 1: reserved. bit 0: tmr0 , timer 0 interrupt mask. the state of the mask bit of the timer interrupt control register
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 59 poll status register offset : 26h 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 s4 - s0 reserved ireq (master mode) the poll status (pollst) register mirrors the current state of the poll register. the pollst register can be read without affecting the current interrupt request. bit 15: ireq , interrupt request. set 1: if an interrupt is pe nding. the s4-s0 field contains valid data. bit 14-5: reserved. bit 4-0: s4-s0 , poll status. indicate the interrupt type of the highest priority pending interrupt. poll register offset : 24h 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 s4 - s0 reserved ireq (master mode) when the poll register is read, the curre nt interrupt is acknowledged and the next interrupt takes its place in the poll regist er. bit 15: ireq , interrupt request. set 1: if an interrupt is pe nding. the s4-s0 field contains valid data. bit 14-5: reserved. bit 4-0: s4-s0 , poll status. indicates the interrupt type of the highest priority pending interrupt. end-of-interrupt register offset : 22h 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 s4 - s0 nspec reserved (master mode) bit 15: nspec , non-specific eoi. set 1: indicate non-specific eoi. set 0: indicate the speci fic eoi interrupt type in s4-s0. bit 14-5: reserved. bit 4-0: s4-s0 , source eoi type. specify the eoi type of the interrupt that is currently being processed. note: we suggest the specific eoi is the most secure method to use for resetting in-service bit.
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 60 specific end-of-interrupt register offset : 22h 0 reset value : 0000h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 00000000000 l2l1l0 (slave mode) bit 15-3: reserved. bit 2-0: l2-l0, interrupt type. encoded values indicate the priority of th e is (interrupt service) bit to reset. writes to these bits cause an eoi to be issu ed for the interrupt type in slave mode. interrupt vector register offset : 20h 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 t4 - t0 0 0000000 0 0 0 ( slave mode) bit 15-8: reserved bit 7-3: t4-t0, interrupt type. the following interrupt types of slave mode can be programmed. timer 2 interrupt controller: (t4, t3, t2, t1, t0, 1, 0, 1)b timer 1 interrupt controller: (t4, t3, t2, t1, t0, 1, 0, 0)b dma 1 interrupt controller: (t4, t3, t2, t1, t0, 0, 1, 1)b dma 0 interrupt controller: (t4, t3, t2, t1, t0, 0, 1, 0)b timer 0 interrupt controller: (t4, t3, t2, t1, t0, 0, 0, 0)b bit 2-0: reserved
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 61 15. dma unit the dma controller provides the data tran sfer between the memory and peripherals without the intervention of the cpu. there are two dma channels in the dma unit. each channel can accept dma request s from one of three sources: external pins (drq0 for channel 0 or drq1 for cha nnel 1), serial ports (port 0 or port 1), or timer 2 overflow. the data transfer from sources to destinations can be memory to memory, memory to i/o, i/o to i/o, or i/o to memory. either bytes or words can be transferred to or from even or odd addre sses and two bus cycles are necessary (read s from sources and writes to destinations) for each data transfer. dma control logic adder control logic 20-bit adder/subtractor c8h-transfer counter channel 0 c6h,c4h-destination address channel 0 c2h,c0h-source address channel 0 d8h-transfer counter channel 1 d6h,d4h-destination address channel 1 d2h,d0h-source address channel 1 request arbitration logic int interrupt request cah.8-channel 0 dah.8-channel 1 channel control register1,dah channel control register0,cah internal address/data bus timer 2 request drq0 drq1 tdrq cah.4-channel 0 dah.4-channel 1 20 bit 20 bit 16 bit dma unit block serial port0 serial port1 15.1 dma operation every dma transfer consists of two bus cycles (see figure of typical dma transfer) and the two bus cycles cannot be separated by a bus hold request, a refresh request or another dm a request. the registers (cah, c8h, c6h, c4h, c2h, c0h, dah, d8h, d6h, d4h, d2h and d0h) are used to configure and operate the two dma channels.
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 62 clkouta ale a19-a0 ad7-ad0 rd wr t1 t2 t3 t4 t1 t2 t3 t4 address address address data address data typical dma trarsfer dma0 control register offset : cah (dma0) 0 reset value : ----- 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tc sinc sdec dinc ddec st chg ext tdrq p syn0 syn1 int b/w sm/io dm/io bit 15: dm / io , destination address space select. set 1: the destination address is in memory space. set 0: the destination address is in i/o space. bit 14: ddec , destination decrement. set 1: the destination address is automatically decremente d after each transfer. . the b /w (bit 0) bit determines the decr emented value which is by 1. when both of the ddec and dinc bits are set to 1, the address remains constant. set 0: disable the decrement function. bit 13: dinc , destination increment. set 1: the destination address is automatically incremente d after each transfer. the b /w (bit 0) bit determines the in cremented value which is by 1. set 0: disable the increment function. bit 12: sm/ io , source address space select. set 1: the source address is in memory space. set 0: the source address is in i/o space bit 11: sdec , source decrement. set 1: the source address is au tomatically decremente d after each transfer. the b /w (bit 0) bit determines the decrem ented value which is by 1. when both of the sdec and sinc bits
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 63 are set to 1, the address remains constant. set 0: disable the decrement function. bit 10: sinc , source increment. set 1: the source address is au tomatically incremente d after each transfer. the b /w (bit 0) bit determines the in cremented value which is by 1. set 0: disable the increment function bit 9: tc , terminal count. set 1: the synchronized dma transfer is termin ated when the dma transfer count register reaches 0. set 0: the synchronized dma transfer is termin ated when the dma transfer count register reaches 0. the unsynchronized dma transfer is always terminated when the dma transfer count register reaches 0, regardless of the setting of this bit. bit 8: int , interrupt. set 1: dma unit generates an interrupt request when the transfer count is completed. the tc bit must be set to 1 to generate an interrupt. bit 7-6: syn1-syn0 , synchronization type selection. syn1 , syn0 -- synchronization type 0 , 0 -- unsynchronized 0 , 1 -- source synchronized 1 , 0 -- destination synchronized 1 , 1 -- reserved bit 5: p , priority. set 1: it selects high priority for this channel when both dma 0 and dm a 1 are transferred at the same time. bit 4: tdrq , timer enable/disable request set 1: enable the dma requests from timer 2. set 0: disable the dma requests from timer 2. bit 3: ext , external interrupt enable bit. set 1: the external pin is an interrupt pin (dma0 f unction is disabled). set 0: the external pin is a drq pin. bit 2: chg , changed start bit. this bit must be set to 1 when the st bit is modified. bit 1: st , start/stop dma channel. set 1: start the dma channel set 0: stop the dma channel bit 0: b /w , byte/word select. this bit is fixed to low.
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 64 dma0 transfer count register offset : c8h (dma0) 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tc15 - tc0 bit 15-0 : tc15-tc0, dma 0 transfer count. the value of this register is decremented by 1 after each transfer. dma0 destination address high register offset : c6h (dma0) 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved dda19 - dda16 bit 15-4 : reserved bit 3-0: dda19-dda16 , high dma 0 destination address. these bits are mapped to a19- a16 during a dma transfer when the destination address is in memory space or i/o space. if the destination addr ess is in i/o space (64kbytes), these bits must be programmed to 0000b. dma0 destination address low register offset : c4h (dma0) 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 dda15 - dda0 bit 15-0: dda15-dda0 , low dma 0 destination address. these bits are mapped to a15- a0 during a dma transfer. the value of (dda19-dda0) will be incremen ted or decremented by 2 after each dma transfer. dma0 source address high register offset : c2h (dma0) 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 dsa19 - dsa16 bit 15-4 : reserved bit 3-0: dsa19-dsa16 , high dma 0 source address. these bits are mapped to a19- a16 during a dma transfer when the source address is in memory space or i/o space. if the source address is in i/o space (64kbytes), these bits must be programmed to 0000b.
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 65 dma0 source address low register offset : c0h (dma0) 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 dsa15 - dsa0 bit 15-0: dsa15-dsa0 , low dma 0 source address. these bits are mapped to a15- a0 during a dma transfer. the value of (dsa19-dsa0) will be increm ented or decremented by 2 after each dma transfer. dma1 control register offset : dah (dma1) 0 reset value : ----- 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tc sinc sdec dinc ddec st chg ext tdrq p syn0 syn1 int b/w sm/io dm/io the definitions of bit 15-0 for dma1 are the same as those of bit 15-0 of register cah for dma0. dma1 transfer count register offset : d8h (dma1) 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tc15 - tc0 bit 15-0 : tc15-tc0, dma 1 transfer count. the value of this register is decremented by 1 after each transfer. dma1 destination address high register offset : d6h (dma1) 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved dda19 - dda16 bit 15-4 : reserved bit 3-0: dda19-dda16 , high dma 1 destination address. these bits are mapped to a19- a16 during a dma transfer when the destination address is in memory space or i/o sp ace. if the destination address is in i/o space (64kbytes), these bits must be programmed to 0000b. dma1 destination address low register offset : d4h (dma1) 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 dda15 - dda0 bit 15-0: dda15-dda0 , low dma 1 destination address. these bits are mapped to a15- a0 during a dma transfer. the value of (dda19-dda0) will be incremented or decremented by 2 after each dma transfer.
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 66 dma1 source address high register offset : d2h (dma1) 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 dsa19 - dsa16 reserved bit 15-4 : reserved bit 3-0: dsa19-dsa16 , high dma 1 source address. these bits are mapped to a19- a16 during a dma transfer when the source address is in memory space or i/o space. if the source address is in i/o space (64kbytes), these bits must be programmed to 0000b. dma1 source address low register offset : d0h (dma1) 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 dsa15 - dsa0 bit 15-0: dsa15-dsa0 , low dma 1 source address. these bits are mapped to a15- a0 during a dma transfer. the value of (dsa19-dsa0) will be incremente d or decremented by 2 after each dma transfer. 15.2 external requests external dma requests are asserted on the drq pins. the drq pins are sample d on the falling edge of clkouta. it takes a minimum of four clocks before the dma cycle is initiated by the bus inte rface. the dma request is cleared four clocks before the end of the dma cycle. and no dma acknowle dge is provided, since the chip-selects (mcsx and pcsx) can be programmed to be active for a given bl ock of memory or i/o space, and the dma source and destination address registers can be programmed to point to the same given block. dma transfer can be either source- or destination- synchronized, and it can also be unsynchronized. the source-synchronized transfer figure shows the typical source-synchronized transfer which provides the source device at least three clock cycles from the time it is acknowledged to de-assert its drq line.
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 67 clkouta drq(case1) drq(case2) fetch cycle fetch cycle source-synchronized transfers t1 t2 t3 t4 t1 t2 t3 t4 notes: case1 : current source synchronized transfer will not be immediately followed by another dma transfer. case2 : current source synchronized transfer will be immediately followed by antoher dma transfer. the destination-synchroniz ed transfer figure shows the typical destinatio n-synchronized transfer which differs from a source-synchronized transfer in wh ich two idle states are added to the end of the depos it cycle. the two idle states extend the dma cycle to allow the destination device to de-assert its drq pin four clocks before the end of the cycle. if the two idle states were not inserted, the de stination device would not have tim e to de-assert its drq signal. clkouta drq(case1) drq(case2) fetch cycle fetch cycle destination-synchronized transfers t1 t2 t3 t4 t1 t2 t3 t4 ti ti netes: case1 : current destination synchronized transfer will not be immediately followed by another dma transfer. case2 : current destination synchronized transfer will be immediately followed by another dma transfer.
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 68 15.3 serial port/dma transfer the serial port data can be dma transfer to or from memory (or io) space. and the b /w bit of dma control register must be set 1 for byte transfer. the map address of transmit da ta register is written to the dm a destination address register and the memory (or i/o) address is written to the dma source address register when data ar e transmitted. the map address of receive data register is written to the dma source address register and the me mory (or i/o) address is written to the dma destination address register wh en data are received. software is used to program the serial port control register to perform th e serial port/dma transfer. when a dma channel is in use by a serial port, the corresponding external dma request signal is deactivated. for dma to the serial port, t he dma channel should be configured as de stination-synchronized. for dma from the se rial port, the dma channel should be configured as source-synchronized.
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 69 16. timer control unit there are three 16-bit programmabl e timers in the R8830. the timer operation is i ndependent of the cpu. the three timers can be programmed as a timer element or as a counter element. time rs 0 and 1 are each connected to two external pins (tmrin0, tmrout0, tmrin1 and tmrout1) which can be used to count or time external events, or used to generate variable-duty-cycle waveforms. timer 2 is not connected to any external pins. it can be used as a pre-scaler to timer 0 and timer 1 or as a dma request source. bit 15: en , enable bit. set 1: the timer 0 is enabled. set 0: the timer 0 is inhibited from counting. the inh bit must be set to 1 when the en bit is written, and the inh and en bits must be in the same write. bit 14: inh , inhibit bit. this bit allows selective updating the en bit. the inh bit must be set to 1 when the en bit is counter element & control logic microprocessor clock 50h,timer 0 count register 58h,timer 1 count register 52h,54h,timer0 maxcount compare register 5ah,5ch,timer 1 maxcount compare register 62h,timer 2 compare register 60h,timer 2 count register interrupt request 5eh,timer 1 control register 56h,timer 0 control register internal address/data bus tmrout1 tmrout2 16 bit 16 bit timer / counter unit block 16 bit dma request 66h,timer 2 control register tmrin1 tmrin0 (timer2) (timer0,1,2) offset : 56h 0 reset value : 0000h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 timer 0 mode / control register cont alt ext p rtg mc 0 0 0 0 0 riu int en 0 inh
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 70 written, and both the inh and en bits must be in the same write. this bit is not stored and always read as 0. bit 13: int , interrupt bit. set 1: an interrupt request is ge nerated when the count register equals a ma ximum count. if the timer is configured in dual max-count mode, an interrupt is genera ted each time when the count reaches max-count a or max-count b set 0: timer 0 will not issue interrupt requests. bit 12: riu , register in use bit. set 1: the maxcount compare b register of timer 0 is being used set 0: the maxcount compare a register of timer 0 is being used bit 11-6 : reserved. bit 5: mc , maximum count bit. when the timer reaches its maximum count, the mc bit will be set to 1 by h/w. in dual maxcount mode, this bit is set each time when either maxcount compare a or maxcount compare b register is reached. this bit is set regardless of the int bit (56h.13). bit 4: rtg , re-trigger bit. this bit defines th e control function by the input signa l of the tmrin0 pin. when ext=1 (56h.2), this bit is ignored. set 1: timer0 count register (50h) counts internal events; reset the counti ng on every tmrin0 input signal from low to high (rising edge trigger). set 0: low input holds the timer 0 count register (50h) value; high input enables the coun ting which counts internal events. the definition of setting the (ext, rtg) (0, 0) ? timer0 counts the intern al events if the tmrin0 pin remains high. (0, 1) ? timer0 counts the internal events; count register reset on every risi ng transition on the tmrin0 pin (1, x) ? the tmrin0 pin input acts as a clock source and timer0 count register is incr emented by one every external clock. bit 3: p , pre-scaler bit. this bit and ext ( 56h.2) define the timer0 clock source. the definition of setting the (ext, p ) (0, 0) ? timer0 count register is increm ented by one every four internal processor clock. (0, 1) ? timer0 count register is incr emented by one which is pre-scaled by timer 2. (1, x) ? the tmrin0 pin input acts as a clock s ource and timer0 count register is incremented by one every external clock. bit 2: ext , external clock bit. set 1: timer0 clock source from external set 0: timer0 clock source from internal bit 1: alt , alternate compare bit. this bit controls whether the timer runs in single or dual maximum count mode. set 1: specify dual maximum count mode. in this mode the timer counts to maxcount compare a and resets the count register to 0. then the timer counts to maxcount compare b, resets the count regist er to 0 again, and starts over with maxcount compare a.
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 71 set 0: specify single maximum count mode. in this mode the timer c ounts to the value contained in maxcount compare a and reset to 0. then the tim er counts to maxcount compare a again. maxcount compare b is not used in this mode. bit 0: cont , continuous mode bit. set 1: the timer runs continuously. set 0: the timer will halt after each counting to the maximum count and the en bit will be cleared. bit 15 ? 0: tc15-tc0 , timer 0 count value. this register contains the curre nt count of timer 0. the count is incremented by one every four internal processor cloc ks, pre-scaled by the timer 2, or in cremented by one every external clock which is through configuring the exte rnal clock select bit based on the tmrin0 signal. bit 15-0: tc15 ? tc0 , timer 0 compare a value. bit 15-0: tc15 ? tc0 , timer 0 compare b value. these bit definitions for timer 1 are the sa me as those of register 56h for timer0. offset : 50h 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 timer 0 count register tc15 - tc0 offset : 52h 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 timer 0 maxcount compare a register tc15 - tc0 offset : 54h 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 timer 0 maxcount compare b register tc15 - tc0 offset : 5eh 0 reset value : 0000h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 timer 1 mode / control register cont alt ext p rtg mc 0 0 0 0 0 riu int en 0 inh
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 72 bit 15 ? 0: tc15-tc0 , timer 1 count value. this register contains the curre nt count of timer 1. the count is incremented by one every four internal processor cloc ks, pre-scaled by the timer 2, or in cremented by one every external clock which is through configuring the exte rnal clock select bit based on the tmrin1 signal. bit 15-0: tc15 ? tc0 , timer 1 compare a value. bit 15-0: tc15 ? tc0 , timer 1 compare b value. bit 15: en , enable bit. set 1: timer 2 is enabled. set 0: timer 2 is inhibited from counting. the inh bit must be set to 1 when th e en bit is written, and the inh and en bits must be in the same write. bit 14: inh , inhibit bit. this bit allows selective updating the en bit. the inh bit must be set to 1 when the en bit is written, and both the inh and en bits must be in the same write. this bit is not stored and always read as 0. bit 13: int , interrupt bit. offset : 58h 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 timer 1 count register tc15 - tc0 offset : 5ah 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 timer 1 maxcount compare a register tc15 - tc0 offset : 66h 0 reset value : 0000h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 timer 2 mode / control register cont 0 0 0 0 mc 0 0 0 0 0 0 int en 0 inh offset : 5ch 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 timer 1 maxcount compare b register tc15 - tc0
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 73 set 1: an interrupt request is generate d when the count register equals a maximum count. set 0: timer 2 will not issue interrupt request. bit 12-6 : reserved. bit 5: mc , maximum count bit. when the timer reaches its maximum c ount, the mc bit will be set to 1 by h/w. this bit is set regardless of the int bit (66h.13). bit 4-1 : reserved. bit 0: count , continuous mode bit. set 1: timer is continuously r unning when timer reaches the maximum count. set 0: the en bit (66h.15) is cleared and the timer is held after each timer count reaches the maximum count. bit 15 ? 0: tc15-tc0 , timer 2 count value. this register contains the curre nt count of timer 2. the count is incremented by one every four internal processor clocks. bit 15-0: tc15 ? tc0 , timer 2 compare a value. 16.1 timer/counter unit output mode timers 0 and 1 can use one maximum count value or two maximum count values. timer 2 can use only one maximum count value. timer 0 and timer1 can be configured to si ngle or dual maximum compare count mode. the tmrout0 or tmrout1 signals can be used to genera ted waveforms of various duty cycles. offset : 60h 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 timer 2 count register tc15 - tc0 offset : 62h 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 timer 2 maxcount compare a register tc15 - tc0
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 74 maxcount a maxcount b maxcount a maxcount b dual maximum count mode single maximum count mode maxcount a 1t maxcount a 1t maxcount a * 1t:one microprocessor clock timer/counter unit output modes
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 75 17. watchdog timer the R8830 has one independent watc hdog timer, which is programmable. the watchdog timer is active after reset and the timeout count is with a maximum count value. the keye d sequence (3333h, cccch) must be written to the register (e6h) first, then the new configuration to th e watchdog timer control register. it is a single write, so every one writing to watchdo g timer control register must follow this rule. when the watchdog timer activates, an internal counter is counting. if this internal count is over the watchdog timer duration, the watchdog timeout happens. th e keyed sequence (aaa ah, 5555h) must be written to the register (e6h) to reset the internal count and prevent the watchdog timeout. the internal count should be reset before the watchdog timer timeout period is modified to ensure that an immediate timeout will not occur. bit 15: ena , enable watchdog timer. set 1: enable watchdog timer. set 0: disable watchdog timer. bit 14: wrst , watchdog reset. set 1: wdt generates a system reset when wdt timeout count is reached. set 0: wdt generates an nmi interrupt when wdt timeout count is reached if the nmiflag bit is 0. if the nmiflag bit is 1, the wdt will generate a system reset when timeout. bit 13: rstflag , reset flag. when watchdog timer reset event occurs, this bit will be set to 1 by hardware. this bit will be cleared by any keyed sequence written to this register or external reset. this bit is 0 after an external reset or 1 afte r watchdog timer reset. bit 12: nmiflag , nmi flag. after wdt generates an nmi interrupt, this bit will be set to 1 by h/w. this bit will be cleared by any keyed sequence written to this register. bit 11-8: reserved. bit 7-0: count , timeout count. the count setting determines the duration of the watchdog timer timeout interval. a. the duration equation : duration = exponent 2 / frequency b. the exponent of the count setting: (bit 7, bit 6, bit 5, bit 4, bit 3, bit 2, bit 1, bit 0) = (exponent) ( 0 , 0 , 0 , 0, 0 , 0 , 0 , 0 ) = (n/a) ( x , x , x , x, x , x , x , x ) = ( 10 ) watchdog timer control register offset : e6h 0 reset value : c080h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 nmiflag rstflag wrst ena count res
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 76 (x , x , x , x, x , x , 1 , 0 ) = ( 20 ) (x , x , x , x, x , 1 , 0 , 0 ) = ( 21 ) (x , x , x , x, 1 , 0 , 0 , 0 ) = ( 22 ) (x , x , x , 1, 0 , 0 , 0 , 0 ) = ( 23 ) (x , x , 1 , 0, 0 , 0 , 0 , 0 ) = ( 24 ) ( x , 1 , 0 , 0, 0 , 0 , 0 , 0 ) = ( 25 ) ( 1 , 0 , 0 , 0, 0 , 0 , 0 , 0 ) = ( 26 ) c. watchdog timer duration reference table: frequency\exponent 10 20 21 22 23 24 25 26 20 mhz 51 us 52 ms 104 ms 209 ms 419 ms 838 ms 1.67 s 3.35 s 25 mhz 40 us 41 ms 83 ms 167 ms 335 ms 671 ms 1.34 s 2.68 s 33 mhz 30 us 31 ms 62 ms 125 ms 251 ms 503 ms 1.00 s 2.01 s 40 mhz 25 us 26 ms 52 ms 104 ms 209 ms 419 ms 838 ms 1.67 s
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 77 18. asynchronous serial port the R8830 has two asynchronous serial ports , which provide the txd and rxd pins for the full duplex bi-directional data transfer and with handshaking signals cts , enrx , rts and rt r . the serial ports support: 9- bit, 8-bit or 7-bit data transfer; odd parity, even parity, or no pa rity; 1 stop bits; error detection; dma transfers through the serial port; multi-dro p protocol (9-bit) support; double buf fers for transmit and receive. the receive/transmit clock is based on the microprocessor clock. the serial port can be used in power-saved mode, but the transfer rate must be adjusted to corr ectly reflect the new internal operating frequency. software is used to program the registers (80h, 82h, 84h, 86h and 88h ? for port 0; 10h, 12h, 14h, 16h and 18h ? for port 1) to configure the asynchronous serial port. 18.1 serial port flow control the two serial ports are provided with two data pi ns (rxd and txd) and two flow control signals ( rts and rt r ). hardware flow control is enabled when the fc bit in the serial port control register is set. and the flow control signals are configured by software to suppor t several different protocols. transmit data register(84h),(14h) transmit hold register transmit shift regoster receive data register(86h),(16h) receive buffer receive shift register txd control logic control register(80h),(10h) status register(82h),(12h) baud rate divisor register(88h),(18h) interrupt request rxd internal address/data bus serial port block diagram 16 bit 8 bit 8 bit 16 bit 16 bit 8 bit 8 bit rts rtr cts enrx
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 78 18.1.1 dce/dte protocol the R8830 can be as a dce (data communication equipment) or as a dte (data terminal equipment). this protocol provides flow control where one serial port is receiving data and other serial port is sendi ng data. to implement the dce device, the enrx bit should be set and the rts bit should be cl eared for the associated serial port. to implement the dte device, the enrx bit should be cleared and the rts bit should be set for the associated serial port. the enrx and rts bits are in the register f2h. the dce/dte protocol is asymmetric in terface since the dte device cannot signal th e dce device that is ready to receive data, and the dce cannot send the request to send signals. the dce/dte protocol communication step: a. dte send data to dce b. rts signal is asserted by dte when data is available. c. the rts signal is interpreted by the dce device as a request to enable its receiver. d. the dce asserts the rt r signal to response that dce is ready to receive data. 18.1.2 cts/rtr protocol the serial port can be programmed as a cts/rts protocol by cleari ng both enrx bit and rts bit. this protocol is a symmetric interface, which provides flow contro l when both ports are se nding and receiving data. dce dte enrx rts rtr cts dce/dte protocol connection rts:request to send cts:clear to send rtr:ready to receive enrx:enable receiver request rtr cts cts/rtr protocol connection cts:clear to send rtr:ready to receive cts rtr
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 79 18.2 dma transfer to/from a serial port function dma transfers to the serial port function as destination-synchronized dma transfers. a new transfer is requested when the transmit holding register is empty. when the port is confi gured for dma transmits, the corresponding transmit interrupt is disabled regardless of the txie bit setting. dma transfers from the serial port function as source-synchroni zed dma transfers. a new tran sfer is requested when the receive buffer contains valid data. when the port is confi gured for dma receives, the co rresponding receive interrupt is disabled regardless of the rxie bit setting. the dma request is generated internally wh en a dma channel is being used for serial port transfers. and the drq0 or drq1 is not active when a serial port dma tr ansfers. hardware handshaking may be us ed in conjunction with serial port dma transfers. 18.3 the asynchronous modes description there are 4 modes operation in the asynchronous serial port. mode1: mode 1 is the 8-bit asynchronous communications mode. each frame consists of a start bit, eight data bits and a stop bit. when parity is used, the eighth data bit becomes the parity bit. mode 2: mode 2 is used together with mode 3 for multiprocessor communications over a common serial link. in mode 2, the rx machine will not complete a reception unless the ninth data b it is a one. any character receive d with the ninth bit equal to zero is ignored. no flags are set, no interrupts occur and no data is transferred to receive data register. in mode 3, characte rs are received regardless of the state of the ninth data bit. mode 3: mode 3 is the 9-bit asynchronous communications mode. mode 3 is the same as mode 1 except that a frame contains nine data bits. the ninth data bit becomes th e parity bit when the parity feature is enabled. mode 4: mode 4 is the 7-bit asynchronous communications mode. each frame consists of a start bit, seven data bits and a stop bit. parity bit is not available in mode 4. bit 15-13: dma , dma control field. these bits configure th e serial port for use with dma transfers. dma control bits (bit 15, bit 14, bit 13)b --- receive --- transmit ( 0, 0, 0 ) --- no dma --- no dma ( 0, 0, 1 ) --- dma 0 --- dma 1 serial port 0 control register offset : 80h 0 reset value : 0000h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 dma rise brk tb8 fc txie rxie tmode rmodd evn pe mode
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 80 ( 0, 1, 0 ) --- dma 1 --- dma 0 ( 0, 1, 1 ) --- n/a --- n/a ( 1, 0, 0 ) --- dma 0 --- no dma ( 1, 0, 1 ) --- dma 1 --- no dma ( 1, 1, 0 ) --- no dma --- dma 0 ( 1, 1, 1 ) --- no dma --- dma 1 bit 12: rsie , receive status interrupt enable. an exception occurs during data recepti on or error detection occurs will generate an interrupt. set 1: enable the serial por t 0 to generate an interrupt request. bit 11: brk , send break. set this bit to 1, the txd pin always drives low. long break: the txd is driven low for greater than (2m+3) bit times; short break: the txd is driv en low for greater than m bit times; * m= start bit + data bits number + parity bit + stop bit bit 10: tb8 , transmit bit 8. this bit is transmitted as the ninth data b it in mode 2 and mode 3. this bit is cleared after every transmission. bit 9: fc , flow control enable. set 1: enable the hardware flow control for serial port 0. set 0 : disable the hardware flow control for serial port 0. bit 8 : txie , transmitter ready interrupt enable. wh en the transmit holding register is empty (the thre bit in status register is set), an interrupt will occur. set 1: enable the interrupt. set 0: disable the interrupt. bit 7: rxie, receive data ready interrupt enable. when the receiver buffer contains valid data (the rdr bit in status register is set), it will generate an interrupt. set 1: enable the interrupt. set 0: disable the interrupt. bit 6 : tmode , transmit mode. set 1: enable the tx machines. set 0: disable the tx machines. bit 5: rmode , received mode. set 1: enable the rx machines. set 0: disable the rx machines. bit 4: evn, even parity. this bit is valid only when the pe bit is set. set 1: the even parity checking is enforced (even number of 1s in frame).
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 81 set 0: odd parity checking is enforced (odd number of 1s in frame). bit 3: pe , parity enable. set 1: enable the parity checking. set 0: disable the parity checking. bit 2-0: mode , mode of operation. ( bit 2, bit 1, bit 0) mode da ta bits parity bits stop bits ( 0 , 0 , 1) mode 1 7 or 8 1 or 0 1 ( 0 , 1 , 0) mode 2 9 n/a 1 ( 0 , 1 , 1) mode 3 8 or 9 1 or 0 1 ( 1 , 0 , 0) mode 4 7 n/a 1 the serial port 0 status register provides information about the curre nt status of the serial port 0. bit 15-11 : reserved. bit 10: brk1 , long break detected. this bit should be reset by software. when a long break is detected, this bit will be set high. bit 9: brk0 , short break detected. this b it should be reset by software. when a short break is detected, this bit will be set high bit 8: rb8, received bit 8. this bit s hould be reset by software. this bit contains the ninth da ta bit received in mode 2 and mode 3. bit 7: rdr, received data ready. read only. the received data register contains valid data. this bit is set high and can onl y be reset by reading the serial port 0 receive register. bit 6: thre , transmit hold register empty. read only. when the transmit hold register is ready to accept data, this b it will be set. this bit will be reset when data is writte n to the transmit hold register. bit 5: fer , framing error detected. this b it should be reset by software. this bit is set when a framing error is detected. bit 4: oer , overrun error detected. this b it should be reset by software. this bit is set when an overrun error is detected. bit 3: per , parity error detected. this b it should be reset by software. this bit is set when a parity error (for mode 1 and mode 3) is detected. bit 2: temt , transmitter empty. this bit is read only. serial port 0 status register offset : 82h 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 brk1 temt hs0 res reserved brk0 rb8 rdr thre fer oer per
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 82 when the transmit shift regist er is empty, this bit will be set. bit 1: hs0 , handshake signal 0. this bit is read only. this bit reflects the i nverted value of the external 0 cts pin. bit 0: reserved. bit 15-8 : reserved bit 7-0 : tdata, transmit data. this register is written by soft ware with data to be transmitted on the serial port 0. bit 15-8 : reserved bit 7-0: rdata , received data. the rdr bit should be read as 1 befo re the rdata register is read to avoid reading invalid data. bit 15-0: bauddiv , baud rate divisor. the general formula for baud rate divisor is baud rate = microprocessor clock / (16 x bauddiv). for example, when the microprocessor clock is 22.1184mhz and the bauddiv=12 (decimal), the baud rate of serial port is 115.2k. serial port 0 transmit register offset : 84h 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved tdata serial port 0 receive register offset : 86h 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 rdata reserved serial port 0 baud rate divisor register offset : 88h 0 reset value : 0000h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 bauddiv
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 83 these bit definitions are the same as those of register 80h. these bit definitions are the same as those of register 82h. these bit definitions are the same as those of register 84h. these bit definitions are the same as those of register 86h. these bit definitions are the same as those of register 88h. serial port 1 control register offset : 10h 0 reset value : 0000h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 dma rise brk tb8 fc txie rxie tmode rmodd evn pe mode serial port 1 status register offset : 12h 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 brk1 temt hs0 res reserved brk0 rb8 rdr thre fer oer per serial port 1 transmit register offset : 14h 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved tdata serial port 1 receive register offset : 16h 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 rdata reserved serial port 1 baud rate divisor register offset : 18h 0 reset value : 0000h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 bavddiv
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 84 19. pio unit the R8830 provides 32 programmable i/o si gnals, which are multi-functional pins with other normal function signals. software is used to program the registers (7ah, 78h, 76h, 74h, 72h and 70h) to configure the mu lti-functional pins for pio or normal function. 19.1 pio multi-function pin list table pio no. pin no. multi function reset status/pio internal resistor 0 72 tmrin1 input with 10k pull-up 1 73 tmrout1 input with 10k pull-down 2 59 pcs6 /a2 input with 10k pull-up 3 60 pcs5 /a1 input with 10k pull-up 4 48 dt/ r normal operation/ input with 10k pull-up 5 49 den normal operation/ input with 10k pull-up 6 46 srdy normal operation/ input with 10k pull-down 7 22 a17 normal operation/ input with 10k pull-up 8 20 a18 normal operation/ input with 10k pull-up 9 19 a19 normal operation/ input with 10k pull-up 10 74 tmrout0 input with 10k pull-down 11 75 tmrin0 input with 10k pull-up 12 77 drq0/int5 input with 10k pull-up 13 76 drq1/int6 input with 10k pull-up 14 50 0 mcs input with 10k pull-up 15 51 1 mcs input with 10k pull-up 16 66 0 pcs input with 10k pull-up dq d q oe write pdata vcc vcc for internal pull-up for internal pull-down pin "0":un-normal function normal data in read pdata microprocessor clock pio direction pio mode normal function pio data in/out pio pin operation diagram
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 85 17 65 1 pcs input with 10k pull-up 18 63 2 pcs / 1 cts / 1 enrx input with 10k pull-up 19 62 3 pcs / 1 rts / 1 rt r input with 10k pull-up 20 3 0 rts / 0 rtr input with 10k pull-up 21 100 0 cts / 0 enrx input with 10k pull-up 22 2 txd0 input with 10k pull-down 23 1 rxd0 input with 10k pull-down 24 68 2 mcs input with 10k pull-up 25 69 3 mcs / rfsh input with 10k pull-up 26 97 uzi input with 10k pull-up 27 98 txd1 input with 10k pull-up 28 99 rxd1 input with 10k pull-up 29 96 s6/ clkdiv input with 10k pull-up 30 52 int4 input with 10k pull-up 31 54 int2 input with 10k pull-up bit 15- 0: pdata31-pdata16 , pio data bits. these bits pdata31- pdata16 are mapped to the pio31 ?pio16 which indicate the driven level when the pio pin is as an output or reflect the extern al level when the pio pin is as an input . bit 15-0: pdir 31- pdir16 , pio direction register. set 1: configure the pio pin as an input. set 0: configure the pio pin as an output or as normal pin function. offset : 7ah 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pdata (31 - 16) pio data 1 register offset : 78h 0 reset value : ffffh 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pdir (31 - 16) pio direction 1 register
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 86 bit 15-0: pmode31-pmode16 , pio mode bit. the definitions of the pio pins are configured by the combination of pio mode a nd pio direction. the pio pins are programmed individually. the definition (pio mode , pio direction) fo r pio pin function: ( 0 , 0 ) ? normal operation , ( 0 , 1 ) ? pio input with pull-up/pull-down ( 1 , 0 ) ? pio output , ( 1 , 1 ) -- pio input without pull-up/pull-down bit 15-0: pdata15- pdata0 : pio data bus. these bits pdata15- pdata0 map to the pio15 ?pio0 which indicate the driven level when the pio pin is as an output or reflect the external le vel when the pio pin is as an input. bit 15-0: pdir 15- pdir0 , pio direction register. set 1: configure the pio pin as an input. set 0: configure the pio pin as an output or as normal pin function. offset : 76h 0 reset value : 0000h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pmode (31 - 16) pio mode 1 register offset : 74h 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pdata (15 - 0) pio data 0 register offset : 72h 0 reset value : ffffh 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pdir (15 - 0) pio direction 0 register
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 87 bit 15-0: pmode15-pmode0 , pio mode bit. offset : 70h 0 reset value : 0000h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pmode (15 - 0) pio mode 0 register
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 88 20. psram control unit the psram interface is provided by the r 8830 and the refresh control unit automatica lly generates refresh bus cycles. the refresh control unit uses the internal micr oprocessor clock as an operating source cloc k. if the power-saved mode is enabled, the refresh control unit must be programmed to reflect the new clock rate. software is used to programs the registers (e0, e2 and e4) to control the refresh control unit operation. bit 15-9 : m6-m0, refresh base. m6-m0 are mapped to a19-a13 of the 20-bit memory refresh address. bit 8-0 : reserved. bit 15-9 : reserved bit 8-0: rc8-rc0, refresh counter reload value. bit 15: e , enable rcu. set 1: enable the refresh counter unit set 0: disable the refresh counter unit. bit 14-9 : reserved bit 8-0: t8-t0 , refresh count. read only bits and these bits present the value of the down counter which triggers refresh requests. memory partition register offset : e0h 0 reset value : 0000h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 m6 - m0 0 0 0 0 0 0 0 0 0 clock prescaler register offset : e2h 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 0 0 0 0 0 rc8 - rc0 enable rcu register offset : e4h 0 reset value : 0000h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 0 0 0 0 e t8 - t0
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 89 21. instruction set opcodes and clock cycles function format clocks notes data transfer instructions mov = move register to register/memory 1000100w mod reg r/m 1/1 register/memory to register 1000101w mod reg r/m 1/6 immediate to register/memory 1100011w mod 000 r/m data data if w=1 1/1 immediate to register 1011w reg data data if w=1 1 memory to accumulator 1010000w addr-low addr-high 6 accumulator to memory 1010001w addr-low addr-high 1 register/memory to segment register 10001110 mod 0 reg r/m 3/8 segment register to register/memory 10001100 mod 0 reg r/m 2/2 push = push memory 11111111 mod 110 r/m 8 register 01010 reg 3 segment register 000reg110 2 immediate 011010s0 data data if s=0 1 pop = pop memory 1000 1111 mod 000 r/m 8 register 01011 reg 6 segment register 000 reg 111 (reg ? 01) 8 pusha = push all 01100000 36 popa = pop all 01100001 44 xchg = exchange register/memory 1000011w mod reg r/m 3/8 register with accumulator 10010 reg 3 xtal = translate byte to al 11010111 10 in = input from fixed port 1110010w port 12 variable port 1110110w 12 out = output from fixed port 1110010w port 12 variable port 1110110w 12 lea = load ea to register 10001101 mod reg r/m 1 lds = load pointer to ds 11000101 mod reg r/m (mod ? 11) 14 les = load pointer to es 11000100 mod reg r/m (mod ? 11) 14 enter = build stack frame 11001000 data-low data-high l l = 0 7 l = 1 11 l > 1 11+10(l-1) leave = tear down stack frame 11001001 7 lahf = load ah with flags 10011111 2 sahf = store ah into flags 10011110 2 pushf = push flags 10011100 2 popf = pop flags 10011101 11 arithmetic instructions add = add
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 90 reg/memory with register to either 000000dw mod reg r/m 1/7 immediate to register/memory 100000sw m od 000 r/m data data if sw=01 1/8 immediate to accumulator 0000010w data data if w=1 1 function format clocks notes adc = add with carry reg/memory with register to either 000100dw mod reg r/m 1/7 immediate to register/memory 100000sw m od 010 r/m data data if sw=01 1/8 immediate to accumulator 0001010w data data if w=1 1 inc = increment register/memory 1111111w mod 000 r/m 1/8 register 01000 reg 1 sub = subtract reg/memory with register to either 001010dw mod reg r/m 1/7 immediate from register/memory 100000sw m od 101 r/m data data if sw=01 1/8 immediate from accumulator 0001110w data data if w=1 1 sbb = subtract with borrow reg/memory with register to either 000110dw mod reg r/m 1/7 immediate from register/memory 100000sw mod 011 r/m 1/8 immediate from accumulator 0001110w data data if w=1 1 dec = decrement register/memory 1111111w mod 001 r/m 1/8 register 01001 reg 1 neg = change sign register/memory 1111011w mod reg r/m 1/8 cmp = compare register/memory with register 0011101w mod reg r/m 1/7 register with register/memory 0011100w mod reg r/m 1/7 immediate with register/memory 100000sw m od 111 r/m data data if sw=01 1/7 immediate with accumulator 00 11110w data data if w=1 1 mul = multiply (unsigned) 1111011w mod 100 r/m register-byte 13 register-word 21 memory-byte 18 memory-word 26 imul = integer multiply (signed) 1111011w mod 101 r/m register-byte 16 register-word 24 memory-byte 21 memory-word 29 register/memory multiply immediate (signed) 011010s1 mod reg r/m data data if s=0 23/28 div = divide (unsigned) 1111011w mod 110 r/m register-byte 18 register-word 26 memory-byte 23 memory-word 31 idiv = integer divide (signed) 1111011w mod 111 r/m register-byte 18 register-word 26 memory-byte 23 memory-word 31 aas = ascii adjust for subtraction 00111111 3 das = decimal adjust for subtraction 0010 1111 2 aaa = ascii adjust for addition 00110111 3 daa = decimal adjust for addition 00100111 2 aad = ascii adjust for divide 11010101 00001010 14 aam = ascii adjust for multiply 11010100 00001010 15 cbw = corrvert byte to word 10011000 2 cwd = convert word to double-word 10011001 2
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 91 function format clocks notes bit manipulation instructuions not = invert register/memory 1111011w mod 010 r/m 1/7 and = and reg/memory and register to either 001000dw mod reg r/m 1/7 immediate to register/memory 1000000w mod 100 r/m data data if w=1 1/8 immediate to accumulator 0010010w data data if w=1 1 or = or reg/memory and register to either 000010dw mod reg r/m 1/7 immediate to register/memory 1000000w mod 001 r/m data data if w=1 1/8 immediate to accumulator 0000110w data data if w=1 1 xor = exclusive or reg/memory and register to either 001100dw mod reg r/m 1/7 immediate to register/memory 1000000w mod 110 r/m data data if w=1 1/8 immediate to accumulator 0011010w data data if w=1 1 test = and function to flags , no result register/memory and register 1000010w mod reg r/m 1/7 immediate data and register/memory 111101 1w mod 000 r/m data data if w=1 1/8 immediate data and accumulator 1010100w data data if w=1 1 sifts/rotates register/memory by 1 1101000w mod ttt r/m 2/8 register/memory by cl 1101001w mod ttt r/m 1+n / 7+n register/memory by count 1100000w mod ttt r/m count 1+n / 7+n string manipulation instructions movs = move byte/word 1010010w 13 ins = input byte/word from dx port 0110110w 13 outs = output byte/word to dx port 0110111w 13 cmps = compare byte/word 1010011w 18 scas = scan byte/word 101011w 13 lods = load byte/word to al/ax 1010110w 13 stos = store byte/word from al/ax 1010101w 7 repeated by count in cx: movs = move byte/word 11110010 1010010w 4+9n ins = input byte/word from dx port 11110010 0110110w 5+9n outs = output byte/word to dx port 11110010 0110111w 5+9n cmps = compare byte/word 1111011z 1010011w 4+18n scas = scan byte/word 1111001z 1010111w 4+13n lods = load byte/word to al/ax 11110010 0101001w 3+9n stos = store byte/word from al/ax 11110100 0101001w 4+3n program transfer instructions conditional transfers ?x jump if: je/jz = equal/zero 01110100 disp 1/9 jl/jnge = less/not greater or equal 01111 100 disp 1/9 jle/jng = less or equal/not greater 01111110 disp 1/9 jc/jb/jnae = carry/below/not above or equal 01110010 disp 1/9 jbe/jna = below or equal/not above 01110110 disp 1/9 jp/jpe = parity/parity even 01111010 disp 1/9 jo = overflow 01110000 disp 1/9 js = sign 01111000 disp 1/9 jne/jnz = not equal/not zero 01110101 disp 1/9 jnl/jge = not less/greater or equal 01111 101 disp 1/9 jnle/jg = not less or equal/greater 01111111 disp 1/9 jnc/jnb/jae = not carry/not below 01110011 disp 1/9 /above or equal jnbe/ja = not below or equal/above 01110111 disp 1/9
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 92 jnp/jpo = not parity/parity odd 01111011 disp 1/9 jno = not overflow 01110001 disp 1/9 jns = not sign 01111001 disp 1/9 function format clocks notes unconditional transfers call = call procedure direct within segment 11101000 disp-low disp-high 11 reg/memory indirect within segment 11111111 mod 010 r/m 12/17 indirect intersegment 11111111 mod 011 r/m (mod ? 11) 25 direct intersegment 10011010 segment offset 18 selector ret = retum from procedure within segment 11000011 16 within segment adding immed to sp 11000010 data-low data-high 16 intersegment 11001011 23 instersegment adding immed to sp 1001010 data-low data-high 23 jmp = unconditional jump short/long 11101011 disp-low 9/9 direct within segment 11101001 disp-low disp-high 9 reg/memory indirect within segment 11111111 mod 100 r/m 11/16 indirect intersegment 11111111 mod 101 r/m (mod ?11) 18 direct intersegment 11101010 segment offset 11 selector iteration control loop = loop cx times 11100010 disp 7/16 loopz/loope = loop while zero/equal 11100001 disp 7/16 loopnz/loopne = loop while not zero/equal 11100000 disp 7/16 jcxz = jump if cx = zero 11100011 disp 7/15 interrupt int = interrupt type specified 11001101 type 41 type 3 11001100 41 into = interrupt on overflow 11001110 43/4 bound = detect value out of range 01100010 mod reg r/m 21-60 iret = interrupt return 11001111 31 processor control instructions clc = clear carry 1111 1000 2 cmc = complement carry 11110101 2 stc = set carry 1111 1001 2 cld = clear direction 11111 100 2 std = set direction 11111 101 2 cli = clear interrupt 1111 1010 5 sti = set interrupt 11111011 5 hlt = halt 11110100 1 wa i t = wait 10011011 1 lock = bus lock prefix 11110000 1 esc = math coprocessor escape 11011mmm mod ppp r/m 1 nop = no operation 10010000 1 segment override prefix cs 00101110 2 ss 00110110 2 ds 00111110 2 es 00100110 2
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 93 22. R8830 execution timings the above instruction timings represent the minimum execution tim e in clock cycles for each in struction. the timings given are based on the following assumptions: 1. the opcode, along with data or displacem ent required for execution, has been pre -fetched and resides in the instruction queue at the time is needed. 2. no wait states or bus holds occur. 3. all word-data is located on even-address boundaries. 4. one risc micro operation ( u op) maps one cycle (according to the pipeline stages described below), except the following case: 4.1 memory read u op needs 6 cycles for bus. 4.2 memory push u op needs 1 cycle if it has no previous memory push u op, and 5 cycles if it has previous memory push or memory write u op. 4.3 mul u op and div of alu function u op for 8-bit operation needs both 8 cy cles, for 16-bit operation needs both 16 cycles. 4.4 all jumps, calls, ret and loopxx inst ructions required to fetch the next in struction for the destination address ( unconditional fetch u op) will need 9 cycles. note : op_r: operand read stage, ea: calculate effective address st age, idle: bus idle stage, t0..t3: bus t0..t3 stage, access: access data from cache memory stage. pipeline stages for single micro operation (one cycle): fetch decode op_r alu wb (for alu function u op) fetch decode ea access wb (for memory function u op) pipeline stages for memory read u op(6 cycles): fetch decode ea access idle t0 t1 t2 t3 wb bus cycle pipeline stages for memory push u op after memory push u op (another 5 cycles): fetch decode ea access idle t0 t1 t2 t3 wb (1 st memory push u op) (2 nd u op) fetch decode ea access access access access access idle t0 t1 t2 t3 wb pipeline stall pipeline stages for unconditional fetch: fetch decode ea access idle t0 t1 t2 t3 fetch ( fetch u op) (next u op) fetch decode ea access access access access access idle t0 t1 t2 t3 wb will be flushed these 9 cycles caused branch penalty fetch decode following stages.. . (new u op)
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 94 23. dc characteristics 23.1 absolute maximum rating symbol rating commercial unit note v term terminal voltage with respect to gnd -0.5~v cc +0.5 v t a ambient temperature 0~+70 c 23.2 recommended dc operating conditions symbol parameter min. typ. max. unit vcc supply voltage 4.75 5 5.25 v gnd ground 0 0 0 v vih input high voltage ( note 1 ) 2.0 --- vcc+0.5 v vih1 input high voltage ( rst ) 3 --- vcc+0.5 v vih2 input high voltage (x1) 3 --- vcc+0.5 v vil input low voltage -0.5 0 0.8 v note 1:the rst and x1 pins are not included. 23.3 dc electrical characteristics symbol parameter test condition min max unit ili input leakage current vcc=vmax vin=gnd to vmax -10 10 ua ili (with 10k pull r) input leakage current with pull_r 10k enable vcc=vmax vin=gnd to vmax -400 400 ua ili (with 50k pull r) input leakage current with pull_r 50k vcc=vmax vin=gnd to vmax -120 120 ua ilo output leakage current vcc=vmax vin=gnd to vmax -10 10 ua vol output low voltage iol=6ma, vcc=vmin. --- 0.4 v voh output high voltage ioh=-6ma, vcc=vmin. 2.4 ---- v icc max operating current vcc=5.25v 40mhz --- 180 ma note 2 : vmax=5.25v vmin=4.75v symbol parameter min. max. unit note f max max operation clock frequency of commercial --- 40 mhz v cc 5%
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 95 24. ac characteristics clkouta a19:a0 s6 ad7:ad0 ale den dtr uzi t1 t2 t3 t4 address data ucs,lcs s2:s0 tw status read cycle pcs x, mcs x address rd 2 1 3 4 5 6 7 8 9 10 12 11 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 96 no. description min max unit 1 clkouta high to a address valid 0 12 ns 2 a address valid to rd low 1.5t-9 ns 3 s6 active delay 0 15 ns 4 s6 inactive delay 0 15 ns 5 ad address valid delay 0 12 ns 6 address hold 0 12 ns 7 data in setup 5 ns 8 data in hold 2 ns 9 ale active delay 0 12 ns 10 ale inactive delay 0 12 ns 11 address valid after ale inactive t/2-5 ns 12 ale width t-5 ns 13 rd active delay 0 12 ns 14 rd pulse width 2t-10 ns 15 rd inactive delay 0 12 ns 16 clkouta high to lcs / ucs valid 0 15 ns 17 ucs / lcs inactive delay 0 15 ns 18 pcs / mcs active delay 0 15 ns 19 pcs / mcs inactive delay 0 15 ns 20 den active delay 0 15 ns 21 den inactive delay 0 15 ns 22 dtr active delay 0 15 ns 23 dtr inactive delay 0 15 ns 24 status active delay 0 15 ns 25 status inactive delay 0 15 ns 26 uzi active delay 0 15 ns 27 uzi inactive delay 0 15 ns 1. t means a clock period time 2. all timing parameters are measured at 1.5v with 50 pf loading on clkouta . all output test conditions are with cl=50 pf
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 97 clkouta a19:a0 s6 ad7:ad0 ale wr den dtr uzi t1 t2 t3 t4 address data ucs,lcs s2:s0 tw status write cycle pcs x, mcs x address wb 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 17 18 20 21 22 23 24 25 26 16 19 27
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 98 no. description min max unit 1 clkouta high to a address valid 0 12 ns 2 a address valid to wr low 1.5t-9 ns 3 s6 active delay 0 15 ns 4 s6 inactive delay 0 15 ns 5 ad address valid delay 0 12 ns 6 address hold ns 7 ale active delay 0 12 ns 8 ale width t-10 ns 9 ale inactive delay 0 12 ns 10 address valid after ale inactive 1/2t-5 ns 11 wr active delay 0 12 ns 12 wr pulse width 2t-10 ns 13 wr inactive delay 0 12 ns 14 wb active delay 0 15 ns 15 wb inactive delay 0 15 ns 16 clkouta high to ucs / lcs valid 0 15 ns 17 ucs / lcs inactive delay 0 15 ns 18 pcs / mcs active delay 0 15 ns 19 pcs / mcs inactive delay 0 15 ns 20 den active delay 0 15 ns 21 den inactive delay 0 15 ns 22 dt r active delay 0 15 ns 23 dt r inactive delay 0 15 ns 24 status active delay 0 15 ns 25 status inactive delay 0 15 ns 26 uzi active delay 0 15 ns 27 uzi inactive delay 0 15 ns
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 99 * the source-synchronized transfer is not fo llowed immediately by another dma transfer no. description min max unit 1 drq is confirmed time 5 ns clkouta a19:a0 ad15:ad0 ale rd wr ucs s2:s0 s6 drq0 dma (1) d00c0 c0000 20000 0 101fc 0 2211 0 2211 * 1fc * 75 7 6 76 den dt/r 1 t1 t2 t3 t4 t1 t2 t3 t4 t1 wb
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 100 * the source-synchronized transfer is follo wed immediately by another dma transfer no. description min max unit 1 drq is confirmed time 2 0 ns clkouta a19:a0 ad15:ad0 ale rd wr wb ucs s2:s0 s6 drq0 dma (2) c0000 c0002 20002 0 5656 den 20000 * * 101fc 2211 0 2211 2 4433 2 4433 1fc 77776 dt/r 1 t1 t2 t3 t4 t1 t2 t3 t4 t1 t2 t3 t4 t1 t2 t3 t4 t1
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 101 no. description min max unit 1 hold setup time 5 0 ns 2 hlda valid delay 0 15 ns 3 hold hold time 2 0 ns 4 hlda valid delay 0 15 ns clkouta a19:a0 ad15:ad0 ale rd wr ucs s2:s0 hlda hold/hlda timing ffff4 zzzzz f0 4 den ffff6 4 hold fff* f0000 fff6 0 fff6 0 b8 77z74 dt/r t1 t2 t3 tw tw tw t4 ti ti ti ti ti ti ti ti ti ti ti ti t1 1 2 3 4 wb
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 102 no. description min max unit 1 ardy resolution transition setup time 5 0 ns 2 ardy active hold time 5 0 ns clkouta ale ardy srdy ardy timing lcs t1 t2 t3 tw tw tw tw tw tw t4 t1 1 2
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 103 no. description min max unit 1 srdy transition setup time 5 0 ns 2 srdy transition hold time 5 0 ns clkouta ale ardy srdy srdy timing lcs t1 t2 t3 tw tw tw tw tw t4 t1 1 2
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 104 25. thermal characteristics ja : thermal resistance from device j unction to ambient temperature p: operation power t a : maximum ambient temperature in operation mode t a =t j ?( p ja ) package/board air flow (m/s) ja 0 48.8 1 44.9 2 42.7 pqfp/2-layer 3 41.9 0 53.6 1 48.9 2 45.5 lqfp/2-layer 3 44.5 0 38.9 1 35.7 2 33.8 pqfp/4-layer 3 33.3 0 42.6 1 38.0 2 36.1 lqfp/4-layer 3 35.3 unit: c/watt recommended storage temperature: ?65c to +125c note: the ic should be mounted on pcb within 7 days after the dr y pack is opened. if the ic is out of dry pack more than 7 days, it should be burned in oven (+ 125c, > 12 hours) before mounted on pcb.
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 105 26. package information 26.1 pqfp 0.089 c seating plane 0.25 min a1 0.22/0.38 b1 b 0.22/0.30/0.33 0.13/0.23 0.13/0.17 c1 c with plating base metal "a" d1 20.00 0.10 d 23.20 0.25 e1 14.00 0.10 e 17.20 0.25 "a" 0.65 bsc 0~7 1.60 ref 0.25 0.88 0.15 l l1 a2 2.75 0.12 detail a 3.40 max 7 typ 15 typ detail a
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 106 26.2 lqfp sealing plane 1 25 26 50 51 75 76 100 0.127(typ) "a" 0.076(max) 0.50(typ) 1.60(max) 1.00(ref) 0.2s(typ) gauge plane 16.00 0.10 14.00 0.10 16.00 0.10 14.00 0.10 1.40 0.05 0.10 0.05 0.22 0.05 0.60 0.15 0 ~ 7 unit:mm
rdc ? risc dsp controller R8830 rdc semiconductor co. final version 1.9 subject to change without notice january 5, 2004 107 27. revision history rev. date history p01 2000/3/8 preliminary release version 0.1 f10 2000/7/31 formal re lease version 1.0 f11 2000/9/1 adding the pin configuration & package information for lqfp package. f12 2000/9/22 modify the serial port 0 baud rate divisor register in page 73 f13 2001/02/22 adding the ac/dc characteristics. f14 2001/3/13 add pqfp and lqfp pin-out table f15 2001/8/8 modify wait-st ate description (p.27) f16 2001/11/30 dc characteristics f17 2001/12/25 modi fy oscillator characteristics f18 2002/05/08 modify wa it-state description f19 2004/01/05 1. modify dc characteristics. 2. add chapters of power save & power down and thermal characteristics.

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